Commit 4bcec913 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc 

Pull more powerpc bits from Ben Herrenschmidt:
 "Here are a few more powerpc bits for this merge window.  The bulk is
  made of two pull requests from Scott and Anatolij that I had missed
  previously (they arrived while I was away).  Since both their branches
  are in -next independently, and the content has been around for a
  little while, they can still go in.

  The rest is mostly bug and regression fixes, a small series of
  cleanups to our pseries cpuidle code (including moving it to the right
  place), and one new cpuidle bakend for the powernv platform.  I also
  wired up the new sched_attr syscalls"

* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (37 commits)
  powerpc: Wire up sched_setattr and sched_getattr syscalls
  powerpc/hugetlb: Replace __get_cpu_var with get_cpu_var
  powerpc: Make sure "cache" directory is removed when offlining cpu
  powerpc/mm: Fix mmap errno when MAP_FIXED is set and mapping exceeds the allowed address space
  powerpc/powernv/cpuidle: Back-end cpuidle driver for powernv platform.
  powerpc/pseries/cpuidle: smt-snooze-delay cleanup.
  powerpc/pseries/cpuidle: Remove MAX_IDLE_STATE macro.
  powerpc/pseries/cpuidle: Make cpuidle-pseries backend driver a non-module.
  powerpc/pseries/cpuidle: Use cpuidle_register() for initialisation.
  powerpc/pseries/cpuidle: Move processor_idle.c to drivers/cpuidle.
  powerpc: Fix 32-bit frames for signals delivered when transactional
  powerpc/iommu: Fix initialisation of DART iommu table
  powerpc/numa: Fix decimal permissions
  powerpc/mm: Fix compile error of pgtable-ppc64.h
  powerpc: Fix hw breakpoints on !HAVE_HW_BREAKPOINT configurations
  clk: corenet: Adds the clock binding
  powerpc/booke64: Guard e6500 tlb handler with CONFIG_PPC_FSL_BOOK3E
  powerpc/512x: dts: add MPC5125 clock specs
  powerpc/512x: clk: support MPC5121/5123/5125 SoC variants
  powerpc/512x: clk: enforce even SDHC divider values
  ...
parents 03c7287d f878f843

Documentation/devicetree/bindings/clock/corenet-clock.txt

0 → 100644
+134 −0
Original line number Diff line number Diff line 
* Clock Block on Freescale CoreNet Platforms



Freescale CoreNet chips take primary clocking input from the external

SYSCLK signal. The SYSCLK input (frequency) is multiplied using

multiple phase locked loops (PLL) to create a variety of frequencies

which can then be passed to a variety of internal logic, including

cores and peripheral IP blocks.

Please refer to the Reference Manual for details.



1. Clock Block Binding



Required properties:

- compatible: Should contain a specific clock block compatible string

	and a single chassis clock compatible string.

	Clock block strings include, but not limited to, one of the:

	* "fsl,p2041-clockgen"

	* "fsl,p3041-clockgen"

	* "fsl,p4080-clockgen"

	* "fsl,p5020-clockgen"

	* "fsl,p5040-clockgen"

	* "fsl,t4240-clockgen"

	* "fsl,b4420-clockgen"

	* "fsl,b4860-clockgen"

	Chassis clock strings include:

	* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks

	* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks

- reg: Describes the address of the device's resources within the

	address space defined by its parent bus, and resource zero

	represents the clock register set

- clock-frequency: Input system clock frequency



Recommended properties:

- ranges: Allows valid translation between child's address space and

	parent's. Must be present if the device has sub-nodes.

- #address-cells: Specifies the number of cells used to represent

	physical base addresses.  Must be present if the device has

	sub-nodes and set to 1 if present

- #size-cells: Specifies the number of cells used to represent

	the size of an address. Must be present if the device has

	sub-nodes and set to 1 if present



2. Clock Provider/Consumer Binding



Most of the bindings are from the common clock binding[1].

 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt



Required properties:

- compatible : Should include one of the following:

	* "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)

	* "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)

	* "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)

	* "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)

	* "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).

		It takes parent's clock-frequency as its clock.

	* "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).

		It takes parent's clock-frequency as its clock.

- #clock-cells: From common clock binding. The number of cells in a

	clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"

	clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.

	For "fsl,qoriq-core-pll-[1,2].0" clocks, the single

	clock-specifier cell may take the following values:

	* 0 - equal to the PLL frequency

	* 1 - equal to the PLL frequency divided by 2

	* 2 - equal to the PLL frequency divided by 4



Recommended properties:

- clocks: Should be the phandle of input parent clock

- clock-names: From common clock binding, indicates the clock name

- clock-output-names: From common clock binding, indicates the names of

	output clocks

- reg: Should be the offset and length of clock block base address.

	The length should be 4.



Example for clock block and clock provider:

/ {

	clockgen: global-utilities@e1000 {

		compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";

		ranges = <0x0 0xe1000 0x1000>;

		clock-frequency = <133333333>;

		reg = <0xe1000 0x1000>;

		#address-cells = <1>;

		#size-cells = <1>;



		sysclk: sysclk {

			#clock-cells = <0>;

			compatible = "fsl,qoriq-sysclk-1.0";

			clock-output-names = "sysclk";

		}



		pll0: pll0@800 {

			#clock-cells = <1>;

			reg = <0x800 0x4>;

			compatible = "fsl,qoriq-core-pll-1.0";

			clocks = <&sysclk>;

			clock-output-names = "pll0", "pll0-div2";

		};



		pll1: pll1@820 {

			#clock-cells = <1>;

			reg = <0x820 0x4>;

			compatible = "fsl,qoriq-core-pll-1.0";

			clocks = <&sysclk>;

			clock-output-names = "pll1", "pll1-div2";

		};



		mux0: mux0@0 {

			#clock-cells = <0>;

			reg = <0x0 0x4>;

			compatible = "fsl,qoriq-core-mux-1.0";

			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;

			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";

			clock-output-names = "cmux0";

		};



		mux1: mux1@20 {

			#clock-cells = <0>;

			reg = <0x20 0x4>;

			compatible = "fsl,qoriq-core-mux-1.0";

			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;

			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";

			clock-output-names = "cmux1";

		};

	};

  }



Example for clock consumer:



/ {

	cpu0: PowerPC,e5500@0 {

		...

		clocks = <&mux0>;

		...

	};

  }

arch/powerpc/Kconfig

+1 −5
Original line number Diff line number Diff line
@@ -532,6 +532,7 @@ config PPC_16K_PAGES 


config PPC_64K_PAGES

	bool "64k page size" if 44x || PPC_STD_MMU_64 || PPC_BOOK3E_64

	depends on !PPC_FSL_BOOK3E

	select PPC_HAS_HASH_64K if PPC_STD_MMU_64



config PPC_256K_PAGES
@@ -1045,11 +1046,6 @@ config KEYS_COMPAT 


source "crypto/Kconfig"



config PPC_CLOCK

	bool

	default n

	select HAVE_CLK



config PPC_LIB_RHEAP

	bool

arch/powerpc/boot/dts/ac14xx.dts

+7 −0
Original line number Diff line number Diff line
@@ -139,7 +139,14 @@ 
		};

	};



	clocks {

		osc {

			clock-frequency = <25000000>;

		};

	};



	soc@80000000 {

		bus-frequency = <80000000>;	/* 80 MHz ips bus */



		clock@f00 {

			compatible = "fsl,mpc5121rev2-clock", "fsl,mpc5121-clock";

arch/powerpc/boot/dts/mpc5121.dtsi

+112 −1
Original line number Diff line number Diff line
@@ -9,6 +9,8 @@ 
 * option) any later version.

 */



#include <dt-bindings/clock/mpc512x-clock.h>



/dts-v1/;



/ {
@@ -49,6 +51,10 @@ 
		compatible = "fsl,mpc5121-mbx";

		reg = <0x20000000 0x4000>;

		interrupts = <66 0x8>;

		clocks = <&clks MPC512x_CLK_MBX_BUS>,

			 <&clks MPC512x_CLK_MBX_3D>,

			 <&clks MPC512x_CLK_MBX>;

		clock-names = "mbx-bus", "mbx-3d", "mbx";

	};



	sram@30000000 {
@@ -62,6 +68,8 @@ 
		interrupts = <6 8>;

		#address-cells = <1>;

		#size-cells = <1>;

		clocks = <&clks MPC512x_CLK_NFC>;

		clock-names = "ipg";

	};



	localbus@80000020 {
@@ -73,6 +81,17 @@ 
		ranges = <0x0 0x0 0xfc000000 0x04000000>;

	};



	clocks {

		#address-cells = <1>;

		#size-cells = <0>;



		osc: osc {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <33000000>;

		};

	};



	soc@80000000 {

		compatible = "fsl,mpc5121-immr";

		#address-cells = <1>;
@@ -117,9 +136,12 @@ 
		};



		/* Clock control */

		clock@f00 {

		clks: clock@f00 {

			compatible = "fsl,mpc5121-clock";

			reg = <0xf00 0x100>;

			#clock-cells = <1>;

			clocks = <&osc>;

			clock-names = "osc";

		};



		/* Power Management Controller */
@@ -139,12 +161,24 @@ 
			compatible = "fsl,mpc5121-mscan";

			reg = <0x1300 0x80>;

			interrupts = <12 0x8>;

			clocks = <&clks MPC512x_CLK_BDLC>,

				 <&clks MPC512x_CLK_IPS>,

				 <&clks MPC512x_CLK_SYS>,

				 <&clks MPC512x_CLK_REF>,

				 <&clks MPC512x_CLK_MSCAN0_MCLK>;

			clock-names = "ipg", "ips", "sys", "ref", "mclk";

		};



		can@1380 {

			compatible = "fsl,mpc5121-mscan";

			reg = <0x1380 0x80>;

			interrupts = <13 0x8>;

			clocks = <&clks MPC512x_CLK_BDLC>,

				 <&clks MPC512x_CLK_IPS>,

				 <&clks MPC512x_CLK_SYS>,

				 <&clks MPC512x_CLK_REF>,

				 <&clks MPC512x_CLK_MSCAN1_MCLK>;

			clock-names = "ipg", "ips", "sys", "ref", "mclk";

		};



		sdhc@1500 {
@@ -153,6 +187,9 @@ 
			interrupts = <8 0x8>;

			dmas = <&dma0 30>;

			dma-names = "rx-tx";

			clocks = <&clks MPC512x_CLK_IPS>,

				 <&clks MPC512x_CLK_SDHC>;

			clock-names = "ipg", "per";

		};



		i2c@1700 {
@@ -161,6 +198,8 @@ 
			compatible = "fsl,mpc5121-i2c", "fsl-i2c";

			reg = <0x1700 0x20>;

			interrupts = <9 0x8>;

			clocks = <&clks MPC512x_CLK_I2C>;

			clock-names = "ipg";

		};



		i2c@1720 {
@@ -169,6 +208,8 @@ 
			compatible = "fsl,mpc5121-i2c", "fsl-i2c";

			reg = <0x1720 0x20>;

			interrupts = <10 0x8>;

			clocks = <&clks MPC512x_CLK_I2C>;

			clock-names = "ipg";

		};



		i2c@1740 {
@@ -177,6 +218,8 @@ 
			compatible = "fsl,mpc5121-i2c", "fsl-i2c";

			reg = <0x1740 0x20>;

			interrupts = <11 0x8>;

			clocks = <&clks MPC512x_CLK_I2C>;

			clock-names = "ipg";

		};



		i2ccontrol@1760 {
@@ -188,30 +231,48 @@ 
			compatible = "fsl,mpc5121-axe";

			reg = <0x2000 0x100>;

			interrupts = <42 0x8>;

			clocks = <&clks MPC512x_CLK_AXE>;

			clock-names = "ipg";

		};



		display@2100 {

			compatible = "fsl,mpc5121-diu";

			reg = <0x2100 0x100>;

			interrupts = <64 0x8>;

			clocks = <&clks MPC512x_CLK_DIU>;

			clock-names = "ipg";

		};



		can@2300 {

			compatible = "fsl,mpc5121-mscan";

			reg = <0x2300 0x80>;

			interrupts = <90 0x8>;

			clocks = <&clks MPC512x_CLK_BDLC>,

				 <&clks MPC512x_CLK_IPS>,

				 <&clks MPC512x_CLK_SYS>,

				 <&clks MPC512x_CLK_REF>,

				 <&clks MPC512x_CLK_MSCAN2_MCLK>;

			clock-names = "ipg", "ips", "sys", "ref", "mclk";

		};



		can@2380 {

			compatible = "fsl,mpc5121-mscan";

			reg = <0x2380 0x80>;

			interrupts = <91 0x8>;

			clocks = <&clks MPC512x_CLK_BDLC>,

				 <&clks MPC512x_CLK_IPS>,

				 <&clks MPC512x_CLK_SYS>,

				 <&clks MPC512x_CLK_REF>,

				 <&clks MPC512x_CLK_MSCAN3_MCLK>;

			clock-names = "ipg", "ips", "sys", "ref", "mclk";

		};



		viu@2400 {

			compatible = "fsl,mpc5121-viu";

			reg = <0x2400 0x400>;

			interrupts = <67 0x8>;

			clocks = <&clks MPC512x_CLK_VIU>;

			clock-names = "ipg";

		};



		mdio@2800 {
@@ -219,6 +280,8 @@ 
			reg = <0x2800 0x800>;

			#address-cells = <1>;

			#size-cells = <0>;

			clocks = <&clks MPC512x_CLK_FEC>;

			clock-names = "per";

		};



		eth0: ethernet@2800 {
@@ -227,6 +290,8 @@ 
			reg = <0x2800 0x800>;

			local-mac-address = [ 00 00 00 00 00 00 ];

			interrupts = <4 0x8>;

			clocks = <&clks MPC512x_CLK_FEC>;

			clock-names = "per";

		};



		/* USB1 using external ULPI PHY */
@@ -238,6 +303,8 @@ 
			interrupts = <43 0x8>;

			dr_mode = "otg";

			phy_type = "ulpi";

			clocks = <&clks MPC512x_CLK_USB1>;

			clock-names = "ipg";

		};



		/* USB0 using internal UTMI PHY */
@@ -249,6 +316,8 @@ 
			interrupts = <44 0x8>;

			dr_mode = "otg";

			phy_type = "utmi_wide";

			clocks = <&clks MPC512x_CLK_USB2>;

			clock-names = "ipg";

		};



		/* IO control */
@@ -267,6 +336,8 @@ 
			compatible = "fsl,mpc5121-pata";

			reg = <0x10200 0x100>;

			interrupts = <5 0x8>;

			clocks = <&clks MPC512x_CLK_PATA>;

			clock-names = "ipg";

		};



		/* 512x PSCs are not 52xx PSC compatible */
@@ -278,6 +349,9 @@ 
			interrupts = <40 0x8>;

			fsl,rx-fifo-size = <16>;

			fsl,tx-fifo-size = <16>;

			clocks = <&clks MPC512x_CLK_PSC0>,

				 <&clks MPC512x_CLK_PSC0_MCLK>;

			clock-names = "ipg", "mclk";

		};



		/* PSC1 */
@@ -287,6 +361,9 @@ 
			interrupts = <40 0x8>;

			fsl,rx-fifo-size = <16>;

			fsl,tx-fifo-size = <16>;

			clocks = <&clks MPC512x_CLK_PSC1>,

				 <&clks MPC512x_CLK_PSC1_MCLK>;

			clock-names = "ipg", "mclk";

		};



		/* PSC2 */
@@ -296,6 +373,9 @@ 
			interrupts = <40 0x8>;

			fsl,rx-fifo-size = <16>;

			fsl,tx-fifo-size = <16>;

			clocks = <&clks MPC512x_CLK_PSC2>,

				 <&clks MPC512x_CLK_PSC2_MCLK>;

			clock-names = "ipg", "mclk";

		};



		/* PSC3 */
@@ -305,6 +385,9 @@ 
			interrupts = <40 0x8>;

			fsl,rx-fifo-size = <16>;

			fsl,tx-fifo-size = <16>;

			clocks = <&clks MPC512x_CLK_PSC3>,

				 <&clks MPC512x_CLK_PSC3_MCLK>;

			clock-names = "ipg", "mclk";

		};



		/* PSC4 */
@@ -314,6 +397,9 @@ 
			interrupts = <40 0x8>;

			fsl,rx-fifo-size = <16>;

			fsl,tx-fifo-size = <16>;

			clocks = <&clks MPC512x_CLK_PSC4>,

				 <&clks MPC512x_CLK_PSC4_MCLK>;

			clock-names = "ipg", "mclk";

		};



		/* PSC5 */
@@ -323,6 +409,9 @@ 
			interrupts = <40 0x8>;

			fsl,rx-fifo-size = <16>;

			fsl,tx-fifo-size = <16>;

			clocks = <&clks MPC512x_CLK_PSC5>,

				 <&clks MPC512x_CLK_PSC5_MCLK>;

			clock-names = "ipg", "mclk";

		};



		/* PSC6 */
@@ -332,6 +421,9 @@ 
			interrupts = <40 0x8>;

			fsl,rx-fifo-size = <16>;

			fsl,tx-fifo-size = <16>;

			clocks = <&clks MPC512x_CLK_PSC6>,

				 <&clks MPC512x_CLK_PSC6_MCLK>;

			clock-names = "ipg", "mclk";

		};



		/* PSC7 */
@@ -341,6 +433,9 @@ 
			interrupts = <40 0x8>;

			fsl,rx-fifo-size = <16>;

			fsl,tx-fifo-size = <16>;

			clocks = <&clks MPC512x_CLK_PSC7>,

				 <&clks MPC512x_CLK_PSC7_MCLK>;

			clock-names = "ipg", "mclk";

		};



		/* PSC8 */
@@ -350,6 +445,9 @@ 
			interrupts = <40 0x8>;

			fsl,rx-fifo-size = <16>;

			fsl,tx-fifo-size = <16>;

			clocks = <&clks MPC512x_CLK_PSC8>,

				 <&clks MPC512x_CLK_PSC8_MCLK>;

			clock-names = "ipg", "mclk";

		};



		/* PSC9 */
@@ -359,6 +457,9 @@ 
			interrupts = <40 0x8>;

			fsl,rx-fifo-size = <16>;

			fsl,tx-fifo-size = <16>;

			clocks = <&clks MPC512x_CLK_PSC9>,

				 <&clks MPC512x_CLK_PSC9_MCLK>;

			clock-names = "ipg", "mclk";

		};



		/* PSC10 */
@@ -368,6 +469,9 @@ 
			interrupts = <40 0x8>;

			fsl,rx-fifo-size = <16>;

			fsl,tx-fifo-size = <16>;

			clocks = <&clks MPC512x_CLK_PSC10>,

				 <&clks MPC512x_CLK_PSC10_MCLK>;

			clock-names = "ipg", "mclk";

		};



		/* PSC11 */
@@ -377,12 +481,17 @@ 
			interrupts = <40 0x8>;

			fsl,rx-fifo-size = <16>;

			fsl,tx-fifo-size = <16>;

			clocks = <&clks MPC512x_CLK_PSC11>,

				 <&clks MPC512x_CLK_PSC11_MCLK>;

			clock-names = "ipg", "mclk";

		};



		pscfifo@11f00 {

			compatible = "fsl,mpc5121-psc-fifo";

			reg = <0x11f00 0x100>;

			interrupts = <40 0x8>;

			clocks = <&clks MPC512x_CLK_PSC_FIFO>;

			clock-names = "ipg";

		};



		dma0: dma@14000 {
@@ -400,6 +509,8 @@ 
		#address-cells = <3>;

		#size-cells = <2>;

		#interrupt-cells = <1>;

		clocks = <&clks MPC512x_CLK_PCI>;

		clock-names = "ipg";



		reg = <0x80008500 0x100	/* internal registers */

		       0x80008300 0x8>;	/* config space access registers */

arch/powerpc/boot/dts/mpc5125twr.dts

+52 −1
Original line number Diff line number Diff line
@@ -12,6 +12,8 @@ 
 * option) any later version.

 */



#include <dt-bindings/clock/mpc512x-clock.h>



/dts-v1/;



/ {
@@ -54,6 +56,17 @@ 
		reg = <0x30000000 0x08000>;		// 32K at 0x30000000

	};



	clocks {

		#address-cells = <1>;

		#size-cells = <0>;



		osc: osc {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <33000000>;

		};

	};



	soc@80000000 {

		compatible = "fsl,mpc5121-immr";

		#address-cells = <1>;
@@ -87,9 +100,12 @@ 
			reg = <0xe00 0x100>;

		};



		clock@f00 {	// Clock control

		clks: clock@f00 {	// Clock control

			compatible = "fsl,mpc5121-clock";

			reg = <0xf00 0x100>;

			#clock-cells = <1>;

			clocks = <&osc>;

			clock-names = "osc";

		};



		pmc@1000{  // Power Management Controller
@@ -114,18 +130,33 @@ 
			compatible = "fsl,mpc5121-mscan";

			interrupts = <12 0x8>;

			reg = <0x1300 0x80>;

			clocks = <&clks MPC512x_CLK_BDLC>,

				 <&clks MPC512x_CLK_IPS>,

				 <&clks MPC512x_CLK_SYS>,

				 <&clks MPC512x_CLK_REF>,

				 <&clks MPC512x_CLK_MSCAN0_MCLK>;

			clock-names = "ipg", "ips", "sys", "ref", "mclk";

		};



		can@1380 {

			compatible = "fsl,mpc5121-mscan";

			interrupts = <13 0x8>;

			reg = <0x1380 0x80>;

			clocks = <&clks MPC512x_CLK_BDLC>,

				 <&clks MPC512x_CLK_IPS>,

				 <&clks MPC512x_CLK_SYS>,

				 <&clks MPC512x_CLK_REF>,

				 <&clks MPC512x_CLK_MSCAN1_MCLK>;

			clock-names = "ipg", "ips", "sys", "ref", "mclk";

		};



		sdhc@1500 {

			compatible = "fsl,mpc5121-sdhc";

			interrupts = <8 0x8>;

			reg = <0x1500 0x100>;

			clocks = <&clks MPC512x_CLK_IPS>,

				 <&clks MPC512x_CLK_SDHC>;

			clock-names = "ipg", "per";

		};



		i2c@1700 {
@@ -134,6 +165,8 @@ 
			compatible = "fsl,mpc5121-i2c", "fsl-i2c";

			reg = <0x1700 0x20>;

			interrupts = <0x9 0x8>;

			clocks = <&clks MPC512x_CLK_I2C>;

			clock-names = "ipg";

		};



		i2c@1720 {
@@ -142,6 +175,8 @@ 
			compatible = "fsl,mpc5121-i2c", "fsl-i2c";

			reg = <0x1720 0x20>;

			interrupts = <0xa 0x8>;

			clocks = <&clks MPC512x_CLK_I2C>;

			clock-names = "ipg";

		};



		i2c@1740 {
@@ -150,6 +185,8 @@ 
			compatible = "fsl,mpc5121-i2c", "fsl-i2c";

			reg = <0x1740 0x20>;

			interrupts = <0xb 0x8>;

			clocks = <&clks MPC512x_CLK_I2C>;

			clock-names = "ipg";

		};



		i2ccontrol@1760 {
@@ -161,6 +198,8 @@ 
			compatible = "fsl,mpc5121-diu";

			reg = <0x2100 0x100>;

			interrupts = <64 0x8>;

			clocks = <&clks MPC512x_CLK_DIU>;

			clock-names = "ipg";

		};



		mdio@2800 {
@@ -180,6 +219,8 @@ 
			interrupts = <4 0x8>;

			phy-handle = < &phy0 >;

			phy-connection-type = "rmii";

			clocks = <&clks MPC512x_CLK_FEC>;

			clock-names = "per";

		};



		// IO control
@@ -200,6 +241,8 @@ 
			interrupts = <43 0x8>;

			dr_mode = "host";

			phy_type = "ulpi";

			clocks = <&clks MPC512x_CLK_USB1>;

			clock-names = "ipg";

			status = "disabled";

		};
@@ -211,6 +254,9 @@ 
			interrupts = <40 0x8>;

			fsl,rx-fifo-size = <16>;

			fsl,tx-fifo-size = <16>;

			clocks = <&clks MPC512x_CLK_PSC1>,

				 <&clks MPC512x_CLK_PSC1_MCLK>;

			clock-names = "ipg", "mclk";

		};



		// PSC9 uart1 aka ttyPSC1
@@ -220,12 +266,17 @@ 
			interrupts = <40 0x8>;

			fsl,rx-fifo-size = <16>;

			fsl,tx-fifo-size = <16>;

			clocks = <&clks MPC512x_CLK_PSC9>,

				 <&clks MPC512x_CLK_PSC9_MCLK>;

			clock-names = "ipg", "mclk";

		};



		pscfifo@11f00 {

			compatible = "fsl,mpc5121-psc-fifo";

			reg = <0x11f00 0x100>;

			interrupts = <40 0x8>;

			clocks = <&clks MPC512x_CLK_PSC_FIFO>;

			clock-names = "ipg";

		};



		dma@14000 {

CRA Git | Maintained and supported by SUSTech CRA and CCSE