Commit 4ba991d3 authored by David S. Miller's avatar David S. Miller
Browse files

sparc: Detect and handle UltraSPARC-T3 cpu types. 



The cpu compatible string we look for is "SPARC-T3".

As far as memset/memcpy optimizations go, we treat this chip the same
as Niagara-T2/T2+.  Use cache initializing stores for memset, and use
perfetch, FPU block loads, cache initializing stores, and block stores
for copies.

We use the Niagara-T2 perf support, since T3 is a close relative in
this regard.  Later we'll add support for the new events T3 can
report, plus enable T3's new "sample" mode.

For now I haven't added any new ELF hwcap flags.  We probably need
to add a couple, for example:

T2 and T3 both support the population count instruction in hardware.

T3 supports VIS3 instructions, including support (finally) for
partitioned shift.  One can also now move directly between float
and integer registers.

T3 supports instructions meant to help with Galois Field and other HPC
calculations, such as XOR multiply.  Also there are "OP and negate"
instructions, for example "fnmul" which is multiply-and-negate.

T3 recognizes the transactional memory opcodes, however since
transactional memory isn't supported: 1) 'commit' behaves as a NOP and
2) 'chkpt' always branches 3) 'rdcps' returns all zeros and 4) 'wrcps'
behaves as a NOP.

So we'll need about 3 new elf capability flags in the end to represent
all of these things.

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 314ff527

arch/sparc/include/asm/elf_64.h

+4 −2
Original line number Diff line number Diff line
@@ -177,9 +177,11 @@ static inline unsigned int sparc64_elf_hwcap(void) 
		cap |= HWCAP_SPARC_ULTRA3;

	else if (tlb_type == hypervisor) {

		if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 ||

		    sun4v_chip_type == SUN4V_CHIP_NIAGARA2)

		    sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||

		    sun4v_chip_type == SUN4V_CHIP_NIAGARA3)

			cap |= HWCAP_SPARC_BLKINIT;

		if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2)

		if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||

		    sun4v_chip_type == SUN4V_CHIP_NIAGARA3)

			cap |= HWCAP_SPARC_N2;

	}

arch/sparc/include/asm/xor_64.h

+2 −1
Original line number Diff line number Diff line
@@ -65,6 +65,7 @@ static struct xor_block_template xor_block_niagara = { 
#define XOR_SELECT_TEMPLATE(FASTEST) \

	((tlb_type == hypervisor && \

	  (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 || \

	   sun4v_chip_type == SUN4V_CHIP_NIAGARA2)) ? \

	   sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || \

	   sun4v_chip_type == SUN4V_CHIP_NIAGARA3)) ? \

	 &xor_block_niagara : \

	 &xor_block_VIS)

arch/sparc/kernel/cpu.c

+6 −0
Original line number Diff line number Diff line
@@ -474,6 +474,12 @@ static void __init sun4v_cpu_probe(void) 
		sparc_pmu_type = "niagara2";

		break;



	case SUN4V_CHIP_NIAGARA3:

		sparc_cpu_type = "UltraSparc T3 (Niagara3)";

		sparc_fpu_type = "UltraSparc T3 integrated FPU";

		sparc_pmu_type = "niagara3";

		break;



	default:

		printk(KERN_WARNING "CPU: Unknown sun4v cpu type [%s]\n",

		       prom_cpu_compatible);

arch/sparc/kernel/cpumap.c

+1 −0
Original line number Diff line number Diff line
@@ -324,6 +324,7 @@ static int iterate_cpu(struct cpuinfo_tree *t, unsigned int root_index) 
	switch (sun4v_chip_type) {

	case SUN4V_CHIP_NIAGARA1:

	case SUN4V_CHIP_NIAGARA2:

	case SUN4V_CHIP_NIAGARA3:

		rover_inc_table = niagara_iterate_method;

		break;

	default:

arch/sparc/kernel/head_64.S

+31 −0
Original line number Diff line number Diff line
@@ -132,6 +132,8 @@ prom_sun4v_name: 
	.asciz	"sun4v"

prom_niagara_prefix:

	.asciz	"SUNW,UltraSPARC-T"

prom_sparc_prefix:

	.asciz	"SPARC-T"

	.align	4

prom_root_compatible:

	.skip	64
@@ -379,6 +381,22 @@ sun4v_chip_type: 
	sethi	%hi(prom_niagara_prefix), %g7

	or	%g7, %lo(prom_niagara_prefix), %g7

	mov	17, %g3

90:	ldub	[%g7], %g2

	ldub	[%g1], %g4

	cmp	%g2, %g4

	bne,pn	%icc, 89f

	 add	%g7, 1, %g7

	subcc	%g3, 1, %g3

	bne,pt	%xcc, 90b

	 add	%g1, 1, %g1

	ba,pt	%xcc, 91f

	 nop



89:	sethi	%hi(prom_cpu_compatible), %g1

	or	%g1, %lo(prom_cpu_compatible), %g1

	sethi	%hi(prom_sparc_prefix), %g7

	or	%g7, %lo(prom_sparc_prefix), %g7

	mov	7, %g3

90:	ldub	[%g7], %g2

	ldub	[%g1], %g4

	cmp	%g2, %g4
@@ -389,6 +407,15 @@ sun4v_chip_type: 
	 add	%g1, 1, %g1



	sethi	%hi(prom_cpu_compatible), %g1

	or	%g1, %lo(prom_cpu_compatible), %g1

	ldub	[%g1 + 7], %g2

	cmp	%g2, '3'

	be,pt	%xcc, 5f

	 mov	SUN4V_CHIP_NIAGARA3, %g4

	ba,pt	%xcc, 4f

	 nop



91:	sethi	%hi(prom_cpu_compatible), %g1

	or	%g1, %lo(prom_cpu_compatible), %g1

	ldub	[%g1 + 17], %g2

	cmp	%g2, '1'
@@ -397,6 +424,7 @@ sun4v_chip_type: 
	cmp	%g2, '2'

	be,pt	%xcc, 5f

	 mov	SUN4V_CHIP_NIAGARA2, %g4

	

4:

	mov	SUN4V_CHIP_UNKNOWN, %g4

5:	sethi	%hi(sun4v_chip_type), %g2
@@ -514,6 +542,9 @@ niagara_tlb_fixup: 
	 cmp	%g1, SUN4V_CHIP_NIAGARA2

	be,pt	%xcc, niagara2_patch

	 nop

	cmp	%g1, SUN4V_CHIP_NIAGARA3

	be,pt	%xcc, niagara2_patch

	 nop



	call	generic_patch_copyops

	 nop

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