Commit 4b73b6f7 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Rob Herring
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dt-bindings: timer: Use defines instead of numbers in Exynos MCT examples 



Make the examples in Exynos Multi Core Timer bindings more readable and
bring them closer to real DTS by using defines for interrupt flags.
Fix also GIC interrupt type in example for Exynos4412 (from SPI to PPI).

Suggested-by: default avatarMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: default avatarRob Herring <robh@kernel.org>
parent 65eba0db

Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml

+27 −10
Original line number Diff line number Diff line
@@ -57,51 +57,68 @@ examples: 
    // In this example, the IP contains two local timers, using separate

    // interrupts, so two local timer interrupts have been specified,

    // in addition to four global timer interrupts.

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    timer@10050000 {

        compatible = "samsung,exynos4210-mct";

        reg = <0x10050000 0x800>;

        interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>,

                     <0 42 0>, <0 48 0>;

        interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;

    };



  - |

    // In this example, the timer interrupts are connected to two separate

    // interrupt controllers. Hence, an interrupts-extended is needed.

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    timer@101c0000 {

        compatible = "samsung,exynos4210-mct";

        reg = <0x101C0000 0x800>;

        interrupts-extended = <&gic 0 57 0>,

                              <&gic 0 69 0>,

        interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,

                              <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,

                              <&combiner 12 6>,

                              <&combiner 12 7>,

                              <&gic 0 42 0>,

                              <&gic 0 48 0>;

                              <&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,

                              <&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;

    };



  - |

    // In this example, the IP contains four local timers, but using

    // a per-processor interrupt to handle them. Only one first local

    // interrupt is specified.

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    timer@10050000 {

        compatible = "samsung,exynos4412-mct";

        reg = <0x10050000 0x800>;



        interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>,

                     <0 42 0>;

        interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>;

    };



  - |

    // In this example, the IP contains four local timers, but using

    // a per-processor interrupt to handle them. All the local timer

    // interrupts are specified.

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    timer@10050000 {

        compatible = "samsung,exynos4412-mct";

        reg = <0x10050000 0x800>;



        interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>,

                     <0 42 0>, <0 42 0>, <0 42 0>, <0 42 0>;

        interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>;

    };

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