Commit 4b4a2700 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6 

* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6: (41 commits)
  inet_diag: Make sure we actually run the same bytecode we audited.
  netlink: Make nlmsg_find_attr take a const nlmsghdr*.
  fib: fib_result_assign() should not change fib refcounts
  netfilter: ip6_tables: fix information leak to userspace
  cls_cgroup: Fix crash on module unload
  memory corruption in X.25 facilities parsing
  net dst: fix percpu_counter list corruption and poison overwritten
  rds: Remove kfreed tcp conn from list
  rds: Lost locking in loop connection freeing
  de2104x: fix panic on load
  atl1 : fix panic on load
  netxen: remove unused firmware exports
  caif: Remove noisy printout when disconnecting caif socket
  caif: SPI-driver bugfix - incorrect padding.
  caif: Bugfix for socket priority, bindtodev and dbg channel.
  smsc911x: Set Ethernet EEPROM size to supported device's size
  ipv4: netfilter: ip_tables: fix information leak to userland
  ipv4: netfilter: arp_tables: fix information leak to userland
  cxgb4vf: remove call to stop TX queues at load time.
  cxgb4: remove call to stop TX queues at load time.
  ...
parents f69fa764 22e76c84

drivers/isdn/hisax/isar.c

+2 −2
Original line number Diff line number Diff line
@@ -1427,8 +1427,8 @@ modeisar(struct BCState *bcs, int mode, int bc) 
					&bcs->hw.isar.reg->Flags))

					bcs->hw.isar.dpath = 1;

				else {

					printk(KERN_WARNING"isar modeisar analog funktions only with DP1\n");

					debugl1(cs, "isar modeisar analog funktions only with DP1");

					printk(KERN_WARNING"isar modeisar analog functions only with DP1\n");

					debugl1(cs, "isar modeisar analog functions only with DP1");

					return(1);

				}

				break;

drivers/net/atlx/atl1.c

+0 −1
Original line number Diff line number Diff line
@@ -3043,7 +3043,6 @@ static int __devinit atl1_probe(struct pci_dev *pdev, 
	atl1_pcie_patch(adapter);

	/* assume we have no link for now */

	netif_carrier_off(netdev);

	netif_stop_queue(netdev);



	setup_timer(&adapter->phy_config_timer, atl1_phy_config,

		    (unsigned long)adapter);

drivers/net/bnx2x/bnx2x.h

+2 −2
Original line number Diff line number Diff line
@@ -20,8 +20,8 @@ 
 * (you will need to reboot afterwards) */

/* #define BNX2X_STOP_ON_ERROR */



#define DRV_MODULE_VERSION      "1.60.00-3"

#define DRV_MODULE_RELDATE      "2010/10/19"

#define DRV_MODULE_VERSION      "1.60.00-4"

#define DRV_MODULE_RELDATE      "2010/11/01"

#define BNX2X_BC_VER            0x040200



#define BNX2X_MULTI_QUEUE

drivers/net/bnx2x/bnx2x_hsi.h

+8 −1
Original line number Diff line number Diff line
@@ -244,7 +244,14 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ 


	u16 xgxs_config_tx[4];				    /* 0x1A0 */



	u32 Reserved1[57];				    /* 0x1A8 */

	u32 Reserved1[56];				    /* 0x1A8 */

	u32 default_cfg;				    /* 0x288 */

	/*  Enable BAM on KR */

#define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK		      0x00100000

#define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT		      20

#define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED		      0x00000000

#define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED		      0x00100000



	u32 speed_capability_mask2;			    /* 0x28C */

#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK		      0x0000FFFF

#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT		      0

drivers/net/bnx2x/bnx2x_link.c

+42 −15
Original line number Diff line number Diff line
@@ -610,7 +610,7 @@ static u8 bnx2x_bmac_enable(struct link_params *params, 
	/* reset and unreset the BigMac */

	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,

		     (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));

	udelay(10);

	msleep(1);



	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,

		     (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
@@ -3525,13 +3525,19 @@ static u8 bnx2x_8073_config_init(struct bnx2x_phy *phy, 
	DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);



	/* Enable CL37 BAM */

	if (REG_RD(bp, params->shmem_base +

			 offsetof(struct shmem_region, dev_info.

				  port_hw_config[params->port].default_cfg)) &

	    PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {



		bnx2x_cl45_read(bp, phy,

				MDIO_AN_DEVAD,

				MDIO_AN_REG_8073_BAM, &val);

		bnx2x_cl45_write(bp, phy,

				 MDIO_AN_DEVAD,

				 MDIO_AN_REG_8073_BAM, val | 1);



		DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");

	}

	if (params->loopback_mode == LOOPBACK_EXT) {

		bnx2x_807x_force_10G(bp, phy);

		DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
@@ -5302,7 +5308,7 @@ static u8 bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy, 
{

	struct bnx2x *bp = params->bp;

	u16 autoneg_val, an_1000_val, an_10_100_val;

	bnx2x_wait_reset_complete(bp, phy);



	bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,

		      1 << NIG_LATCH_BC_ENABLE_MI_INT);
@@ -5431,6 +5437,7 @@ static u8 bnx2x_8481_config_init(struct bnx2x_phy *phy, 


	/* HW reset */

	bnx2x_ext_phy_hw_reset(bp, params->port);

	bnx2x_wait_reset_complete(bp, phy);



	bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);

	return bnx2x_848xx_cmn_config_init(phy, params, vars);
@@ -5441,7 +5448,7 @@ static u8 bnx2x_848x3_config_init(struct bnx2x_phy *phy, 
				  struct link_vars *vars)

{

	struct bnx2x *bp = params->bp;

	u8 port = params->port, initialize = 1;

	u8 port, initialize = 1;

	u16 val;

	u16 temp;

	u32 actual_phy_selection;
@@ -5450,11 +5457,16 @@ static u8 bnx2x_848x3_config_init(struct bnx2x_phy *phy, 
	/* This is just for MDIO_CTL_REG_84823_MEDIA register. */



	msleep(1);

	if (CHIP_IS_E2(bp))

		port = BP_PATH(bp);

	else

		port = params->port;

	bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,

		       MISC_REGISTERS_GPIO_OUTPUT_HIGH,

		       port);

	msleep(200); /* 100 is not enough */



	bnx2x_wait_reset_complete(bp, phy);

	/* Wait for GPHY to come out of reset */

	msleep(50);

	/* BCM84823 requires that XGXS links up first @ 10G for normal

	behavior */

	temp = vars->line_speed;
@@ -5625,7 +5637,11 @@ static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy, 
				   struct link_params *params)

{

	struct bnx2x *bp = params->bp;

	u8 port = params->port;

	u8 port;

	if (CHIP_IS_E2(bp))

		port = BP_PATH(bp);

	else

		port = params->port;

	bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,

			    MISC_REGISTERS_GPIO_OUTPUT_LOW,

			    port);
@@ -6928,7 +6944,7 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars, 
		  u8 reset_ext_phy)

{

	struct bnx2x *bp = params->bp;

	u8 phy_index, port = params->port;

	u8 phy_index, port = params->port, clear_latch_ind = 0;

	DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);

	/* disable attentions */

	vars->link_status = 0;
@@ -6966,9 +6982,18 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars, 
				params->phy[phy_index].link_reset(

					&params->phy[phy_index],

					params);

			if (params->phy[phy_index].flags &

			    FLAGS_REARM_LATCH_SIGNAL)

				clear_latch_ind = 1;

		}

	}



	if (clear_latch_ind) {

		/* Clear latching indication */

		bnx2x_rearm_latch_signal(bp, port, 0);

		bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,

			       1 << NIG_LATCH_BC_ENABLE_MI_INT);

	}

	if (params->phy[INT_PHY].link_reset)

		params->phy[INT_PHY].link_reset(

			&params->phy[INT_PHY], params);
@@ -6999,6 +7024,7 @@ static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp, 
	s8 port;

	s8 port_of_path = 0;



	bnx2x_ext_phy_hw_reset(bp, 0);

	/* PART1 - Reset both phys */

	for (port = PORT_MAX - 1; port >= PORT_0; port--) {

		u32 shmem_base, shmem2_base;
@@ -7021,7 +7047,8 @@ static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp, 
			return -EINVAL;

		}

		/* disable attentions */

		bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,

		bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +

			       port_of_path*4,

			     (NIG_MASK_XGXS0_LINK_STATUS |

			      NIG_MASK_XGXS0_LINK10G |

			      NIG_MASK_SERDES0_LINK_STATUS |
@@ -7132,7 +7159,7 @@ static u8 bnx2x_8726_common_init_phy(struct bnx2x *bp, 
		(1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));

	REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);



	bnx2x_ext_phy_hw_reset(bp, 1);

	bnx2x_ext_phy_hw_reset(bp, 0);

	msleep(5);

	for (port = 0; port < PORT_MAX; port++) {

		u32 shmem_base, shmem2_base;

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