Commit 4b37ba90 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu 

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: (21 commits)
  m68knommu: convert to using tracehook_report_syscall_*
  m68knommu: some boards use fixed phy for FEC ethernet
  m68knommu: support the external GPIO based interrupts of the 5272
  m68knommu: mask of vector bits in exception word properly
  m68knommu: change to new flag variables
  m68knommu: Fix MCFUART_TXFIFOSIZE for m548x.
  m68knommu: add basic mmu-less m548x support
  m68knommu: .gitignore vmlinux.lds
  m68knommu: stop using __do_IRQ
  m68knommu: rename PT_OFF_VECTOR to PT_OFF_FORMATVEC.
  m68knommu: add support for Coldfire 547x/548x interrupt controller
  m68k{nommu}: Remove unused DEFINE's from asm-offsets.c
  m68knommu: whitespace cleanup in 68328/entry.S
  m68knommu: Document supported chips in intc-2.c and intc-simr.c.
  m68knommu: fix strace support for 68328/68360
  m68knommu: fix default starting date
  arch/m68knommu: Removing dead 68328_SERIAL_UART2 config option
  arch/m68knommu: Removing dead RAM_{16,32}_MB config option
  arch/m68knommu: Removing dead M68KFPU_EMU config option
  arch/m68knommu: Removing dead RELOCATE config option
  ...
parents 229aebb8 55f411de

arch/m68k/include/asm/cacheflush_no.h

+1 −1
Original line number Diff line number Diff line
@@ -29,7 +29,7 @@ 


static inline void __flush_cache_all(void)

{

#ifdef CONFIG_M5407

#if defined(CONFIG_M5407) || defined(CONFIG_M548x)

	/*

	 *	Use cpushl to push and invalidate all cache lines.

	 *	Gas doesn't seem to know how to generate the ColdFire

arch/m68k/include/asm/coldfire.h

+3 −1
Original line number Diff line number Diff line
@@ -32,7 +32,9 @@ 
 */

#define	MCF_MBAR	0x10000000

#define	MCF_MBAR2	0x80000000

#if defined(CONFIG_M520x)

#if defined(CONFIG_M548x)

#define	MCF_IPSBAR	MCF_MBAR

#elif defined(CONFIG_M520x)

#define	MCF_IPSBAR	0xFC000000

#else

#define	MCF_IPSBAR	0x40000000

arch/m68k/include/asm/gpio.h

+6 −1
Original line number Diff line number Diff line
@@ -36,7 +36,8 @@ 
 */

#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \

    defined(CONFIG_M520x) || defined(CONFIG_M523x) || \

    defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)

    defined(CONFIG_M527x) || defined(CONFIG_M528x) || \

    defined(CONFIG_M532x) || defined(CONFIG_M548x)



/* These parts have GPIO organized by 8 bit ports */
@@ -136,6 +137,8 @@ static inline u32 __mcf_gpio_ppdr(unsigned gpio) 
#endif

	else

		return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);

#else

	return 0;

#endif

}
@@ -173,6 +176,8 @@ static inline u32 __mcf_gpio_podr(unsigned gpio) 
#endif

	else

		return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START);

#else

	return 0;

#endif

}

arch/m68k/include/asm/m548xgpt.h

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/*

 * File:	m548xgpt.h

 * Purpose:	Register and bit definitions for the MCF548X

 *

 * Notes:

 *

 */



#ifndef m548xgpt_h

#define m548xgpt_h



/*********************************************************************

*

* General Purpose Timers (GPT)

*

*********************************************************************/



/* Register read/write macros */

#define MCF_GPT_GMS0       0x000800

#define MCF_GPT_GCIR0      0x000804

#define MCF_GPT_GPWM0      0x000808

#define MCF_GPT_GSR0       0x00080C

#define MCF_GPT_GMS1       0x000810

#define MCF_GPT_GCIR1      0x000814

#define MCF_GPT_GPWM1      0x000818

#define MCF_GPT_GSR1       0x00081C

#define MCF_GPT_GMS2       0x000820

#define MCF_GPT_GCIR2      0x000824

#define MCF_GPT_GPWM2      0x000828

#define MCF_GPT_GSR2       0x00082C

#define MCF_GPT_GMS3       0x000830

#define MCF_GPT_GCIR3      0x000834

#define MCF_GPT_GPWM3      0x000838

#define MCF_GPT_GSR3       0x00083C

#define MCF_GPT_GMS(x)     (0x000800+((x)*0x010))

#define MCF_GPT_GCIR(x)    (0x000804+((x)*0x010))

#define MCF_GPT_GPWM(x)    (0x000808+((x)*0x010))

#define MCF_GPT_GSR(x)     (0x00080C+((x)*0x010))



/* Bit definitions and macros for MCF_GPT_GMS */

#define MCF_GPT_GMS_TMS(x)         (((x)&0x00000007)<<0)

#define MCF_GPT_GMS_GPIO(x)        (((x)&0x00000003)<<4)

#define MCF_GPT_GMS_IEN            (0x00000100)

#define MCF_GPT_GMS_OD             (0x00000200)

#define MCF_GPT_GMS_SC             (0x00000400)

#define MCF_GPT_GMS_CE             (0x00001000)

#define MCF_GPT_GMS_WDEN           (0x00008000)

#define MCF_GPT_GMS_ICT(x)         (((x)&0x00000003)<<16)

#define MCF_GPT_GMS_OCT(x)         (((x)&0x00000003)<<20)

#define MCF_GPT_GMS_OCPW(x)        (((x)&0x000000FF)<<24)

#define MCF_GPT_GMS_OCT_FRCLOW     (0x00000000)

#define MCF_GPT_GMS_OCT_PULSEHI    (0x00100000)

#define MCF_GPT_GMS_OCT_PULSELO    (0x00200000)

#define MCF_GPT_GMS_OCT_TOGGLE     (0x00300000)

#define MCF_GPT_GMS_ICT_ANY        (0x00000000)

#define MCF_GPT_GMS_ICT_RISE       (0x00010000)

#define MCF_GPT_GMS_ICT_FALL       (0x00020000)

#define MCF_GPT_GMS_ICT_PULSE      (0x00030000)

#define MCF_GPT_GMS_GPIO_INPUT     (0x00000000)

#define MCF_GPT_GMS_GPIO_OUTLO     (0x00000020)

#define MCF_GPT_GMS_GPIO_OUTHI     (0x00000030)

#define MCF_GPT_GMS_TMS_DISABLE    (0x00000000)

#define MCF_GPT_GMS_TMS_INCAPT     (0x00000001)

#define MCF_GPT_GMS_TMS_OUTCAPT    (0x00000002)

#define MCF_GPT_GMS_TMS_PWM        (0x00000003)

#define MCF_GPT_GMS_TMS_GPIO       (0x00000004)



/* Bit definitions and macros for MCF_GPT_GCIR */

#define MCF_GPT_GCIR_CNT(x)        (((x)&0x0000FFFF)<<0)

#define MCF_GPT_GCIR_PRE(x)        (((x)&0x0000FFFF)<<16)



/* Bit definitions and macros for MCF_GPT_GPWM */

#define MCF_GPT_GPWM_LOAD          (0x00000001)

#define MCF_GPT_GPWM_PWMOP         (0x00000100)

#define MCF_GPT_GPWM_WIDTH(x)      (((x)&0x0000FFFF)<<16)



/* Bit definitions and macros for MCF_GPT_GSR */

#define MCF_GPT_GSR_CAPT           (0x00000001)

#define MCF_GPT_GSR_COMP           (0x00000002)

#define MCF_GPT_GSR_PWMP           (0x00000004)

#define MCF_GPT_GSR_TEXP           (0x00000008)

#define MCF_GPT_GSR_PIN            (0x00000100)

#define MCF_GPT_GSR_OVF(x)         (((x)&0x00000007)<<12)

#define MCF_GPT_GSR_CAPTURE(x)     (((x)&0x0000FFFF)<<16)



/********************************************************************/



#endif /* m548xgpt_h */

arch/m68k/include/asm/m548xsim.h

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/*

 *	m548xsim.h -- ColdFire 547x/548x System Integration Unit support.

 */



#ifndef	m548xsim_h

#define m548xsim_h



#define MCFINT_VECBASE      64



/*

 *      Interrupt Controller Registers

 */

#define MCFICM_INTC0		0x0700		/* Base for Interrupt Ctrl 0 */

#define MCFINTC_IPRH		0x00		/* Interrupt pending 32-63 */

#define MCFINTC_IPRL		0x04		/* Interrupt pending 1-31 */

#define MCFINTC_IMRH		0x08		/* Interrupt mask 32-63 */

#define MCFINTC_IMRL		0x0c		/* Interrupt mask 1-31 */

#define MCFINTC_INTFRCH		0x10		/* Interrupt force 32-63 */

#define MCFINTC_INTFRCL		0x14		/* Interrupt force 1-31 */

#define MCFINTC_IRLR		0x18		/* */

#define MCFINTC_IACKL		0x19		/* */

#define MCFINTC_ICR0		0x40		/* Base ICR register */



/*

 *	Define system peripheral IRQ usage.

 */

#define MCF_IRQ_TIMER		(64 + 54)	/* Slice Timer 0 */

#define MCF_IRQ_PROFILER	(64 + 53)	/* Slice Timer 1 */



/*

 *	Generic GPIO support

 */

#define MCFGPIO_PIN_MAX		0	/* I am too lazy to count */

#define MCFGPIO_IRQ_MAX		-1

#define MCFGPIO_IRQ_VECBASE	-1



/*

 *	Some PSC related definitions

 */

#define MCF_PAR_PSC(x)		(0x000A4F-((x)&0x3))

#define MCF_PAR_SDA		(0x0008)

#define MCF_PAR_SCL		(0x0004)

#define MCF_PAR_PSC_TXD		(0x04)

#define MCF_PAR_PSC_RXD		(0x08)

#define MCF_PAR_PSC_RTS(x)	(((x)&0x03)<<4)

#define MCF_PAR_PSC_CTS(x)	(((x)&0x03)<<6)

#define MCF_PAR_PSC_CTS_GPIO	(0x00)

#define MCF_PAR_PSC_CTS_BCLK	(0x80)

#define MCF_PAR_PSC_CTS_CTS	(0xC0)

#define MCF_PAR_PSC_RTS_GPIO    (0x00)

#define MCF_PAR_PSC_RTS_FSYNC	(0x20)

#define MCF_PAR_PSC_RTS_RTS	(0x30)

#define MCF_PAR_PSC_CANRX	(0x40)



#endif	/* m548xsim_h */

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