drm/amdgpu: handle AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID on gfx10 (4b22e7e3) · Commits · 戴 / test

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+19 −2

Original line number	Diff line number	Diff line
		@@ -4243,6 +4243,22 @@ static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
		unsigned vmid = AMDGPU_JOB_GET_VMID(job);
		u32 control = INDIRECT_BUFFER_VALID \| ib->length_dw \| (vmid << 24);

		/* Currently, there is a high possibility to get wave ID mismatch
		* between ME and GDS, leading to a hw deadlock, because ME generates
		* different wave IDs than the GDS expects. This situation happens
		* randomly when at least 5 compute pipes use GDS ordered append.
		* The wave IDs generated by ME are also wrong after suspend/resume.
		* Those are probably bugs somewhere else in the kernel driver.
		*
		* Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
		* GDS to 0 for this ring (me/pipe).
		*/
		if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
		amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
		amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
		amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
		}

		amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
		BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
		amdgpu_ring_write(ring,
		@@ -4978,7 +4994,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
		2 + /* gfx_v10_0_ring_emit_vm_flush */
		8 + 8 + 8, /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
		.emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_compute */
		.emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
		.emit_ib = gfx_v10_0_ring_emit_ib_compute,
		.emit_fence = gfx_v10_0_ring_emit_fence,
		.emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
		@@ -5011,7 +5027,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
		2 + /* gfx_v10_0_ring_emit_vm_flush */
		8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
		.emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_compute */
		.emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
		.emit_ib = gfx_v10_0_ring_emit_ib_compute,
		.emit_fence = gfx_v10_0_ring_emit_fence_kiq,
		.test_ring = gfx_v10_0_ring_test_ring,
		@@ -5089,6 +5105,7 @@ static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
		case CHIP_NAVI10:
		default:
		adev->gds.gds_size = 0x10000;
		adev->gds.gds_compute_max_wave_id = 0x4ff;
		adev->gds.vgt_gs_max_wave_id = 0x3ff;
		break;
		}

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