Commit 4b0f7305 authored by Maxime Jourdan's avatar Maxime Jourdan Committed by Neil Armstrong
Browse files

clk: meson-g12a: add video decoder clocks 



Add the necessary clock parts for:

 - VDEC_1: used to feed VDEC_1
 - VDEC_HEVC: the "back" part of the VDEC_HEVC block
 - VDEC_HEVCF: the "front" part of the VDEC_HEVC block

In previous SoC generations (GXL, GXBB), there was only one VDEC_HEVC
clock, which got split in two parts for G12A.

Signed-off-by: default avatarMaxime Jourdan <mjourdan@baylibre.com>
Acked-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190319101138.27520-2-mjourdan@baylibre.com
parent 34775209

drivers/clk/meson/g12a.c

+163 −0
Original line number Diff line number Diff line
@@ -1495,6 +1495,151 @@ static struct clk_regmap g12a_vpu = { 
	},

};



/* VDEC clocks */



static const char * const g12a_vdec_parent_names[] = {

	"fclk_div2p5", "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7",

	"hifi_pll", "gp0_pll",

};



static struct clk_regmap g12a_vdec_1_sel = {

	.data = &(struct clk_regmap_mux_data){

		.offset = HHI_VDEC_CLK_CNTL,

		.mask = 0x7,

		.shift = 9,

		.flags = CLK_MUX_ROUND_CLOSEST,

	},

	.hw.init = &(struct clk_init_data){

		.name = "vdec_1_sel",

		.ops = &clk_regmap_mux_ops,

		.parent_names = g12a_vdec_parent_names,

		.num_parents = ARRAY_SIZE(g12a_vdec_parent_names),

		.flags = CLK_SET_RATE_PARENT,

	},

};



static struct clk_regmap g12a_vdec_1_div = {

	.data = &(struct clk_regmap_div_data){

		.offset = HHI_VDEC_CLK_CNTL,

		.shift = 0,

		.width = 7,

		.flags = CLK_DIVIDER_ROUND_CLOSEST,

	},

	.hw.init = &(struct clk_init_data){

		.name = "vdec_1_div",

		.ops = &clk_regmap_divider_ops,

		.parent_names = (const char *[]){ "vdec_1_sel" },

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



static struct clk_regmap g12a_vdec_1 = {

	.data = &(struct clk_regmap_gate_data){

		.offset = HHI_VDEC_CLK_CNTL,

		.bit_idx = 8,

	},

	.hw.init = &(struct clk_init_data) {

		.name = "vdec_1",

		.ops = &clk_regmap_gate_ops,

		.parent_names = (const char *[]){ "vdec_1_div" },

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



static struct clk_regmap g12a_vdec_hevcf_sel = {

	.data = &(struct clk_regmap_mux_data){

		.offset = HHI_VDEC2_CLK_CNTL,

		.mask = 0x7,

		.shift = 9,

		.flags = CLK_MUX_ROUND_CLOSEST,

	},

	.hw.init = &(struct clk_init_data){

		.name = "vdec_hevcf_sel",

		.ops = &clk_regmap_mux_ops,

		.parent_names = g12a_vdec_parent_names,

		.num_parents = ARRAY_SIZE(g12a_vdec_parent_names),

		.flags = CLK_SET_RATE_PARENT,

	},

};



static struct clk_regmap g12a_vdec_hevcf_div = {

	.data = &(struct clk_regmap_div_data){

		.offset = HHI_VDEC2_CLK_CNTL,

		.shift = 0,

		.width = 7,

		.flags = CLK_DIVIDER_ROUND_CLOSEST,

	},

	.hw.init = &(struct clk_init_data){

		.name = "vdec_hevcf_div",

		.ops = &clk_regmap_divider_ops,

		.parent_names = (const char *[]){ "vdec_hevcf_sel" },

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



static struct clk_regmap g12a_vdec_hevcf = {

	.data = &(struct clk_regmap_gate_data){

		.offset = HHI_VDEC2_CLK_CNTL,

		.bit_idx = 8,

	},

	.hw.init = &(struct clk_init_data) {

		.name = "vdec_hevcf",

		.ops = &clk_regmap_gate_ops,

		.parent_names = (const char *[]){ "vdec_hevcf_div" },

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



static struct clk_regmap g12a_vdec_hevc_sel = {

	.data = &(struct clk_regmap_mux_data){

		.offset = HHI_VDEC2_CLK_CNTL,

		.mask = 0x7,

		.shift = 25,

		.flags = CLK_MUX_ROUND_CLOSEST,

	},

	.hw.init = &(struct clk_init_data){

		.name = "vdec_hevc_sel",

		.ops = &clk_regmap_mux_ops,

		.parent_names = g12a_vdec_parent_names,

		.num_parents = ARRAY_SIZE(g12a_vdec_parent_names),

		.flags = CLK_SET_RATE_PARENT,

	},

};



static struct clk_regmap g12a_vdec_hevc_div = {

	.data = &(struct clk_regmap_div_data){

		.offset = HHI_VDEC2_CLK_CNTL,

		.shift = 16,

		.width = 7,

		.flags = CLK_DIVIDER_ROUND_CLOSEST,

	},

	.hw.init = &(struct clk_init_data){

		.name = "vdec_hevc_div",

		.ops = &clk_regmap_divider_ops,

		.parent_names = (const char *[]){ "vdec_hevc_sel" },

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



static struct clk_regmap g12a_vdec_hevc = {

	.data = &(struct clk_regmap_gate_data){

		.offset = HHI_VDEC2_CLK_CNTL,

		.bit_idx = 24,

	},

	.hw.init = &(struct clk_init_data) {

		.name = "vdec_hevc",

		.ops = &clk_regmap_gate_ops,

		.parent_names = (const char *[]){ "vdec_hevc_div" },

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



/* VAPB Clock */



static const char * const g12a_vapb_parent_names[] = {
@@ -2615,6 +2760,15 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = { 
		[CLKID_PCIE_PLL_DCO_DIV2]	= &g12a_pcie_pll_dco_div2.hw,

		[CLKID_PCIE_PLL_OD]		= &g12a_pcie_pll_od.hw,

		[CLKID_PCIE_PLL]		= &g12a_pcie_pll.hw,

		[CLKID_VDEC_1_SEL]		= &g12a_vdec_1_sel.hw,

		[CLKID_VDEC_1_DIV]		= &g12a_vdec_1_div.hw,

		[CLKID_VDEC_1]			= &g12a_vdec_1.hw,

		[CLKID_VDEC_HEVC_SEL]		= &g12a_vdec_hevc_sel.hw,

		[CLKID_VDEC_HEVC_DIV]		= &g12a_vdec_hevc_div.hw,

		[CLKID_VDEC_HEVC]		= &g12a_vdec_hevc.hw,

		[CLKID_VDEC_HEVCF_SEL]		= &g12a_vdec_hevcf_sel.hw,

		[CLKID_VDEC_HEVCF_DIV]		= &g12a_vdec_hevcf_div.hw,

		[CLKID_VDEC_HEVCF]		= &g12a_vdec_hevcf.hw,

		[NR_CLKS]			= NULL,

	},

	.num = NR_CLKS,
@@ -2803,6 +2957,15 @@ static struct clk_regmap *const g12a_clk_regmaps[] = { 
	&g12a_cpu_clk_trace,

	&g12a_pcie_pll_od,

	&g12a_pcie_pll_dco,

	&g12a_vdec_1_sel,

	&g12a_vdec_1_div,

	&g12a_vdec_1,

	&g12a_vdec_hevc_sel,

	&g12a_vdec_hevc_div,

	&g12a_vdec_hevc,

	&g12a_vdec_hevcf_sel,

	&g12a_vdec_hevcf_div,

	&g12a_vdec_hevcf,

};



static const struct meson_eeclkc_data g12a_clkc_data = {

drivers/clk/meson/g12a.h

+7 −1
Original line number Diff line number Diff line
@@ -189,8 +189,14 @@ 
#define CLKID_PCIE_PLL_DCO			198

#define CLKID_PCIE_PLL_DCO_DIV2			199

#define CLKID_PCIE_PLL_OD			200

#define CLKID_VDEC_1_SEL			202

#define CLKID_VDEC_1_DIV			203

#define CLKID_VDEC_HEVC_SEL			205

#define CLKID_VDEC_HEVC_DIV			206

#define CLKID_VDEC_HEVCF_SEL			208

#define CLKID_VDEC_HEVCF_DIV			209



#define NR_CLKS					202

#define NR_CLKS					211



/* include the CLKIDs that have been made part of the DT binding */

#include <dt-bindings/clock/g12a-clkc.h>

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