Commit 4afe8e79 authored Oct 09, 2018 by Suzuki K Poulose Committed by Catalin Marinas Oct 16, 2018

arm64: cpufeature: Trap CTR_EL0 access only where it is necessary

When there is a mismatch in the CTR_EL0 field, we trap
access to CTR from EL0 on all CPUs to expose the safe
value. However, we could skip trapping on a CPU which
matches the safe value.

Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

parent 1602df02

arch/arm64/kernel/cpu_errata.c

+6 −1

Original line number	Diff line number	Diff line
		@@ -99,6 +99,11 @@ has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry,
		static void
		cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *__unused)
		{
		u64 mask = arm64_ftr_reg_ctrel0.strict_mask;

		/* Trap CTR_EL0 access on this CPU, only if it has a mismatch */
		if ((read_cpuid_cachetype() & mask) !=
		(arm64_ftr_reg_ctrel0.sys_val & mask))
		sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
		}

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