Commit 4afaab78 authored by Joonas Lahtinen's avatar Joonas Lahtinen
Browse files

Merge tag 'gvt-next-fixes-2019-12-02' of https://github.com/intel/gvt-linux... 

Merge tag 'gvt-next-fixes-2019-12-02' of https://github.com/intel/gvt-linux

 into drm-intel-next-fixes

gvt-next-fixes-2019-12-02

- Fix cmd parser for MI_ATOMIC (Zhenyu)
- Fix non-priv register access warning on CFL (Fred)

Signed-off-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
From: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191202051711.GZ4196@zhen-hp.sh.intel.com
parents 3ee1a9f5 92b1aa77

drivers/gpu/drm/i915/gvt/cmd_parser.c

+3 −3
Original line number Original line Diff line number Diff line
@@ -1599,9 +1599,9 @@ static int cmd_handler_mi_op_2f(struct parser_exec_state *s) 
	if (!(cmd_val(s, 0) & (1 << 22)))

	if (!(cmd_val(s, 0) & (1 << 22)))

		return ret;

		return ret;





	/* check if QWORD */

	/* check inline data */

	if (DWORD_FIELD(0, 20, 19) == 1)

	if (cmd_val(s, 0) & BIT(18))

		valid_len += 8;

		valid_len = CMD_LEN(9);

	ret = gvt_check_valid_cmd_length(cmd_length(s),

	ret = gvt_check_valid_cmd_length(cmd_length(s),

			valid_len);

			valid_len);

	if (ret)

	if (ret)

drivers/gpu/drm/i915/gvt/handlers.c

+3 −2
Original line number Original line Diff line number Diff line
@@ -460,6 +460,7 @@ static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 
static i915_reg_t force_nonpriv_white_list[] = {

static i915_reg_t force_nonpriv_white_list[] = {

	GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec)

	GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec)

	GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248)

	GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248)

	PS_INVOCATION_COUNT,//_MMIO(0x2348)

	GEN8_CS_CHICKEN1,//_MMIO(0x2580)

	GEN8_CS_CHICKEN1,//_MMIO(0x2580)

	_MMIO(0x2690),

	_MMIO(0x2690),

	_MMIO(0x2694),

	_MMIO(0x2694),
@@ -508,7 +509,7 @@ static inline bool in_whitelist(unsigned int reg) 
static int force_nonpriv_write(struct intel_vgpu *vgpu,

static int force_nonpriv_write(struct intel_vgpu *vgpu,

	unsigned int offset, void *p_data, unsigned int bytes)

	unsigned int offset, void *p_data, unsigned int bytes)

{

{

	u32 reg_nonpriv = *(u32 *)p_data;

	u32 reg_nonpriv = (*(u32 *)p_data) & REG_GENMASK(25, 2);

	int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);

	int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);

	u32 ring_base;

	u32 ring_base;

	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;

	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
@@ -528,7 +529,7 @@ static int force_nonpriv_write(struct intel_vgpu *vgpu, 
			bytes);

			bytes);

	} else

	} else

		gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n",

		gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n",

			vgpu->id, reg_nonpriv, offset);

			vgpu->id, *(u32 *)p_data, offset);





	return 0;

	return 0;

}

}

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