Commit 4aec6ec0 authored Apr 19, 2016 by Frederic Barrat Committed by Michael Ellerman Apr 22, 2016

cxl: Increase timeout for detection of AFU mmio hang



PSL designers recommend a larger value for the mmio hang pulse, 256 us
instead of 1 us. The CAIA architecture states that it needs to be
smaller than 1/2 of the RTOS timeout set in the PHB for outbound
non-posted transactions, which is still (easily) the case here.

Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Acked-by: Ian Munsie <imunsie@au1.ibm.com>
Tested-by: Frank Haverkamp <haver@linux.vnet.ibm.com>
Tested-by: Manoj Kumar <manoj@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

parent e009a7e8

drivers/misc/cxl/pci.c

+3 −1

Original line number	Diff line number	Diff line
		@@ -375,8 +375,10 @@ static int init_implementation_adapter_regs(struct cxl *adapter, struct pci_dev
		return -ENODEV;
		}

		psl_dsnctl = 0x0000900000000000ULL; /* pteupd ttype, scdone */
		psl_dsnctl \|= (0x2ULL << (63-38)); /* MMIO hang pulse: 256 us */
		/* Tell PSL where to route data to */
		psl_dsnctl = 0x0000900002000000ULL \| (chipid << (63-5));
		psl_dsnctl \|= (chipid << (63-5));
		psl_dsnctl \|= (capp_unit_id << (63-13));

		cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl);

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