Commit 4ac7df17 authored by Imre Deak's avatar Imre Deak
Browse files

drm/i915: Move the DPLL vfunc inits after the func defines 



Move the per-platform DPLL and DPLL-manager vfunc initializations right
after the corresponding function definitions.

Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200226203455.23032-5-imre.deak@intel.com
parent 353ad959

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

+60 −60
Original line number Diff line number Diff line
@@ -45,6 +45,21 @@ 
 * commit phase.

 */



struct intel_dpll_mgr {

	const struct dpll_info *dpll_info;



	bool (*get_dplls)(struct intel_atomic_state *state,

			  struct intel_crtc *crtc,

			  struct intel_encoder *encoder);

	void (*put_dplls)(struct intel_atomic_state *state,

			  struct intel_crtc *crtc);

	void (*update_active_dpll)(struct intel_atomic_state *state,

				   struct intel_crtc *crtc,

				   struct intel_encoder *encoder);

	void (*dump_hw_state)(struct drm_i915_private *dev_priv,

			      const struct intel_dpll_hw_state *hw_state);

};



static void

intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv,

				  struct intel_shared_dpll_state *shared_dpll)
@@ -509,6 +524,19 @@ static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = { 
	.get_hw_state = ibx_pch_dpll_get_hw_state,

};



static const struct dpll_info pch_plls[] = {

	{ "PCH DPLL A", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_A, 0 },

	{ "PCH DPLL B", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_B, 0 },

	{ },

};



static const struct intel_dpll_mgr pch_pll_mgr = {

	.dpll_info = pch_plls,

	.get_dplls = ibx_get_dpll,

	.put_dplls = intel_put_dpll,

	.dump_hw_state = ibx_dump_hw_state,

};



static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,

			       struct intel_shared_dpll *pll)

{
@@ -963,6 +991,23 @@ static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs = { 
	.get_hw_state = hsw_ddi_lcpll_get_hw_state,

};



static const struct dpll_info hsw_plls[] = {

	{ "WRPLL 1",    &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL1,     0 },

	{ "WRPLL 2",    &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL2,     0 },

	{ "SPLL",       &hsw_ddi_spll_funcs,  DPLL_ID_SPLL,       0 },

	{ "LCPLL 810",  &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_810,  INTEL_DPLL_ALWAYS_ON },

	{ "LCPLL 1350", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_1350, INTEL_DPLL_ALWAYS_ON },

	{ "LCPLL 2700", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_2700, INTEL_DPLL_ALWAYS_ON },

	{ },

};



static const struct intel_dpll_mgr hsw_pll_mgr = {

	.dpll_info = hsw_plls,

	.get_dplls = hsw_get_dpll,

	.put_dplls = intel_put_dpll,

	.dump_hw_state = hsw_dump_hw_state,

};



struct skl_dpll_regs {

	i915_reg_t ctl, cfgcr1, cfgcr2;

};
@@ -1518,6 +1563,21 @@ static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = { 
	.get_hw_state = skl_ddi_dpll0_get_hw_state,

};



static const struct dpll_info skl_plls[] = {

	{ "DPLL 0", &skl_ddi_dpll0_funcs, DPLL_ID_SKL_DPLL0, INTEL_DPLL_ALWAYS_ON },

	{ "DPLL 1", &skl_ddi_pll_funcs,   DPLL_ID_SKL_DPLL1, 0 },

	{ "DPLL 2", &skl_ddi_pll_funcs,   DPLL_ID_SKL_DPLL2, 0 },

	{ "DPLL 3", &skl_ddi_pll_funcs,   DPLL_ID_SKL_DPLL3, 0 },

	{ },

};



static const struct intel_dpll_mgr skl_pll_mgr = {

	.dpll_info = skl_plls,

	.get_dplls = skl_get_dpll,

	.put_dplls = intel_put_dpll,

	.dump_hw_state = skl_dump_hw_state,

};



static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,

				struct intel_shared_dpll *pll)

{
@@ -1964,66 +2024,6 @@ static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = { 
	.get_hw_state = bxt_ddi_pll_get_hw_state,

};



struct intel_dpll_mgr {

	const struct dpll_info *dpll_info;



	bool (*get_dplls)(struct intel_atomic_state *state,

			  struct intel_crtc *crtc,

			  struct intel_encoder *encoder);

	void (*put_dplls)(struct intel_atomic_state *state,

			  struct intel_crtc *crtc);

	void (*update_active_dpll)(struct intel_atomic_state *state,

				   struct intel_crtc *crtc,

				   struct intel_encoder *encoder);

	void (*dump_hw_state)(struct drm_i915_private *dev_priv,

			      const struct intel_dpll_hw_state *hw_state);

};



static const struct dpll_info pch_plls[] = {

	{ "PCH DPLL A", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_A, 0 },

	{ "PCH DPLL B", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_B, 0 },

	{ },

};



static const struct intel_dpll_mgr pch_pll_mgr = {

	.dpll_info = pch_plls,

	.get_dplls = ibx_get_dpll,

	.put_dplls = intel_put_dpll,

	.dump_hw_state = ibx_dump_hw_state,

};



static const struct dpll_info hsw_plls[] = {

	{ "WRPLL 1",    &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL1,     0 },

	{ "WRPLL 2",    &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL2,     0 },

	{ "SPLL",       &hsw_ddi_spll_funcs,  DPLL_ID_SPLL,       0 },

	{ "LCPLL 810",  &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_810,  INTEL_DPLL_ALWAYS_ON },

	{ "LCPLL 1350", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_1350, INTEL_DPLL_ALWAYS_ON },

	{ "LCPLL 2700", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_2700, INTEL_DPLL_ALWAYS_ON },

	{ },

};



static const struct intel_dpll_mgr hsw_pll_mgr = {

	.dpll_info = hsw_plls,

	.get_dplls = hsw_get_dpll,

	.put_dplls = intel_put_dpll,

	.dump_hw_state = hsw_dump_hw_state,

};



static const struct dpll_info skl_plls[] = {

	{ "DPLL 0", &skl_ddi_dpll0_funcs, DPLL_ID_SKL_DPLL0, INTEL_DPLL_ALWAYS_ON },

	{ "DPLL 1", &skl_ddi_pll_funcs,   DPLL_ID_SKL_DPLL1, 0 },

	{ "DPLL 2", &skl_ddi_pll_funcs,   DPLL_ID_SKL_DPLL2, 0 },

	{ "DPLL 3", &skl_ddi_pll_funcs,   DPLL_ID_SKL_DPLL3, 0 },

	{ },

};



static const struct intel_dpll_mgr skl_pll_mgr = {

	.dpll_info = skl_plls,

	.get_dplls = skl_get_dpll,

	.put_dplls = intel_put_dpll,

	.dump_hw_state = skl_dump_hw_state,

};



static const struct dpll_info bxt_plls[] = {

	{ "PORT PLL A", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL0, 0 },

	{ "PORT PLL B", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },

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