Commit 4a9f45a0 authored by Thomas Gleixner's avatar Thomas Gleixner Committed by Borislav Petkov
Browse files

intel_idle: Convert to new X86 CPU match macros 



The new macro set has a consistent namespace and uses C99 initializers
instead of the grufty C89 ones.

Get rid the of the local macro wrappers for consistency.

Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Reviewed-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Link: https://lkml.kernel.org/r/20200320131510.193755545@linutronix.de
parent 20d320c6

drivers/idle/intel_idle.c

+38 −41
Original line number Diff line number Diff line
@@ -1068,51 +1068,48 @@ static const struct idle_cpu idle_cpu_dnv = { 
};



static const struct x86_cpu_id intel_idle_ids[] __initconst = {

	INTEL_CPU_FAM6(NEHALEM_EP,		idle_cpu_nhx),

	INTEL_CPU_FAM6(NEHALEM,			idle_cpu_nehalem),

	INTEL_CPU_FAM6(NEHALEM_G,		idle_cpu_nehalem),

	INTEL_CPU_FAM6(WESTMERE,		idle_cpu_nehalem),

	INTEL_CPU_FAM6(WESTMERE_EP,		idle_cpu_nhx),

	INTEL_CPU_FAM6(NEHALEM_EX,		idle_cpu_nhx),

	INTEL_CPU_FAM6(ATOM_BONNELL,		idle_cpu_atom),

	INTEL_CPU_FAM6(ATOM_BONNELL_MID,	idle_cpu_lincroft),

	INTEL_CPU_FAM6(WESTMERE_EX,		idle_cpu_nhx),

	INTEL_CPU_FAM6(SANDYBRIDGE,		idle_cpu_snb),

	INTEL_CPU_FAM6(SANDYBRIDGE_X,		idle_cpu_snx),

	INTEL_CPU_FAM6(ATOM_SALTWELL,		idle_cpu_atom),

	INTEL_CPU_FAM6(ATOM_SILVERMONT,		idle_cpu_byt),

	INTEL_CPU_FAM6(ATOM_SILVERMONT_MID,	idle_cpu_tangier),

	INTEL_CPU_FAM6(ATOM_AIRMONT,		idle_cpu_cht),

	INTEL_CPU_FAM6(IVYBRIDGE,		idle_cpu_ivb),

	INTEL_CPU_FAM6(IVYBRIDGE_X,		idle_cpu_ivt),

	INTEL_CPU_FAM6(HASWELL,			idle_cpu_hsw),

	INTEL_CPU_FAM6(HASWELL_X,		idle_cpu_hsx),

	INTEL_CPU_FAM6(HASWELL_L,		idle_cpu_hsw),

	INTEL_CPU_FAM6(HASWELL_G,		idle_cpu_hsw),

	INTEL_CPU_FAM6(ATOM_SILVERMONT_D,	idle_cpu_avn),

	INTEL_CPU_FAM6(BROADWELL,		idle_cpu_bdw),

	INTEL_CPU_FAM6(BROADWELL_G,		idle_cpu_bdw),

	INTEL_CPU_FAM6(BROADWELL_X,		idle_cpu_bdx),

	INTEL_CPU_FAM6(BROADWELL_D,		idle_cpu_bdx),

	INTEL_CPU_FAM6(SKYLAKE_L,		idle_cpu_skl),

	INTEL_CPU_FAM6(SKYLAKE,			idle_cpu_skl),

	INTEL_CPU_FAM6(KABYLAKE_L,		idle_cpu_skl),

	INTEL_CPU_FAM6(KABYLAKE,		idle_cpu_skl),

	INTEL_CPU_FAM6(SKYLAKE_X,		idle_cpu_skx),

	INTEL_CPU_FAM6(XEON_PHI_KNL,		idle_cpu_knl),

	INTEL_CPU_FAM6(XEON_PHI_KNM,		idle_cpu_knl),

	INTEL_CPU_FAM6(ATOM_GOLDMONT,		idle_cpu_bxt),

	INTEL_CPU_FAM6(ATOM_GOLDMONT_PLUS,	idle_cpu_bxt),

	INTEL_CPU_FAM6(ATOM_GOLDMONT_D,		idle_cpu_dnv),

	INTEL_CPU_FAM6(ATOM_TREMONT_D,		idle_cpu_dnv),

	X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EP,		&idle_cpu_nhx),

	X86_MATCH_INTEL_FAM6_MODEL(NEHALEM,		&idle_cpu_nehalem),

	X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_G,		&idle_cpu_nehalem),

	X86_MATCH_INTEL_FAM6_MODEL(WESTMERE,		&idle_cpu_nehalem),

	X86_MATCH_INTEL_FAM6_MODEL(WESTMERE_EP,		&idle_cpu_nhx),

	X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EX,		&idle_cpu_nhx),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_BONNELL,	&idle_cpu_atom),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_BONNELL_MID,	&idle_cpu_lincroft),

	X86_MATCH_INTEL_FAM6_MODEL(WESTMERE_EX,		&idle_cpu_nhx),

	X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE,		&idle_cpu_snb),

	X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE_X,	&idle_cpu_snx),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_SALTWELL,	&idle_cpu_atom),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT,	&idle_cpu_byt),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_MID,	&idle_cpu_tangier),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT,	&idle_cpu_cht),

	X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE,		&idle_cpu_ivb),

	X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X,		&idle_cpu_ivt),

	X86_MATCH_INTEL_FAM6_MODEL(HASWELL,		&idle_cpu_hsw),

	X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X,		&idle_cpu_hsx),

	X86_MATCH_INTEL_FAM6_MODEL(HASWELL_L,		&idle_cpu_hsw),

	X86_MATCH_INTEL_FAM6_MODEL(HASWELL_G,		&idle_cpu_hsw),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_D,	&idle_cpu_avn),

	X86_MATCH_INTEL_FAM6_MODEL(BROADWELL,		&idle_cpu_bdw),

	X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_G,		&idle_cpu_bdw),

	X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X,		&idle_cpu_bdx),

	X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D,		&idle_cpu_bdx),

	X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L,		&idle_cpu_skl),

	X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE,		&idle_cpu_skl),

	X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L,		&idle_cpu_skl),

	X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE,		&idle_cpu_skl),

	X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X,		&idle_cpu_skx),

	X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL,	&idle_cpu_knl),

	X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM,	&idle_cpu_knl),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT,	&idle_cpu_bxt),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS,	&idle_cpu_bxt),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D,	&idle_cpu_dnv),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D,	&idle_cpu_dnv),

	{}

};



#define INTEL_CPU_FAM6_MWAIT \

	{ X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_MWAIT, 0 }



static const struct x86_cpu_id intel_mwait_ids[] __initconst = {

	INTEL_CPU_FAM6_MWAIT,

	X86_MATCH_VENDOR_FAM_FEATURE(INTEL, 6, X86_FEATURE_MWAIT, NULL),

	{}

};

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