Commit 4a775263 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'amlogic-dt64-2' of...

Merge tag 'amlogic-dt64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt

arm64: dts: amlogic: updates for v5.9 (round 2)
- new board: WeTek Core2
- audio playback support on more boards
- add GPU DVFS

* tag 'amlogic-dt64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
  arm64: dts: amlogic: meson-g12: add the Mali OPP table and use DVFS
  arm64: dts: amlogic: meson-gxm: add the Mali OPP table and use DVFS
  arm64: dts: amlogic: meson-gx: add the Mali-450 OPP table and use DVFS
  arm64: dts: meson: add support for the WeTek Core 2
  dt-bindings: arm: amlogic: add support for the WeTek Core 2
  arm64: dts: meson: add audio playback to khadas-vim3l
  arm64: dts: meson: add audio playback to odroid-c4
  arm64: dts: meson: update spifc node name on Khadas VIM3/VIM3L
  ARM: dts: meson: Align L2 cache-controller nodename with dtschema
  arm64: dts: meson-gxl-s805x: reduce initial Mali450 core frequency
  arm64: dts: meson: add missing gxl rng clock
  soc: amlogic: meson-gx-socinfo: Fix S905X3 and S905D3 ID's

Link: https://lore.kernel.org/r/7h8sf8671u.fsf@baylibre.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 33c56eda 916a0edc
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+1 −0
Original line number Diff line number Diff line
@@ -121,6 +121,7 @@ properties:
              - libretech,aml-s912-pc
              - nexbox,a1
              - tronsmart,vega-s96
              - wetek,core2
          - const: amlogic,s912
          - const: amlogic,meson-gxm

+1 −1
Original line number Diff line number Diff line
@@ -11,7 +11,7 @@
	#size-cells = <1>;
	interrupt-parent = <&gic>;

	L2: l2-cache-controller@c4200000 {
	L2: cache-controller@c4200000 {
		compatible = "arm,pl310-cache";
		reg = <0xc4200000 0x1000>;
		cache-unified;
+1 −0
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@@ -41,6 +41,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q201.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-rbox-pro.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-libretech-pc.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-wetek-core2.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-sm1-sei610.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-sm1-khadas-vim3l.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-c4.dtb
+34 −15
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@@ -52,6 +52,39 @@
		secure-monitor = <&sm>;
	};

	gpu_opp_table: gpu-opp-table {
		compatible = "operating-points-v2";

		opp-124999998 {
			opp-hz = /bits/ 64 <124999998>;
			opp-microvolt = <800000>;
		};
		opp-249999996 {
			opp-hz = /bits/ 64 <249999996>;
			opp-microvolt = <800000>;
		};
		opp-285714281 {
			opp-hz = /bits/ 64 <285714281>;
			opp-microvolt = <800000>;
		};
		opp-399999994 {
			opp-hz = /bits/ 64 <399999994>;
			opp-microvolt = <800000>;
		};
		opp-499999992 {
			opp-hz = /bits/ 64 <499999992>;
			opp-microvolt = <800000>;
		};
		opp-666666656 {
			opp-hz = /bits/ 64 <666666656>;
			opp-microvolt = <800000>;
		};
		opp-799999987 {
			opp-hz = /bits/ 64 <799999987>;
			opp-microvolt = <800000>;
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
@@ -2362,21 +2395,7 @@
			interrupt-names = "job", "mmu", "gpu";
			clocks = <&clkc CLKID_MALI>;
			resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;

			/*
			 * Mali clocking is provided by two identical clock paths
			 * MALI_0 and MALI_1 muxed to a single clock by a glitch
			 * free mux to safely change frequency while running.
			 */
			assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
					  <&clkc CLKID_MALI_0>,
					  <&clkc CLKID_MALI>; /* Glitch free mux */
			assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>,
						 <0>, /* Do Nothing */
						 <&clkc CLKID_MALI_0>;
			assigned-clock-rates = <0>, /* Do Nothing */
					       <800000000>,
					       <0>; /* Do Nothing */
			operating-points-v2 = <&gpu_opp_table>;
			#cooling-cells = <2>;
		};
	};
+61 −0
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2017 BayLibre SAS
 * Author: Neil Armstrong <narmstrong@baylibre.com>
 */

/ {
	gpu_opp_table: opp-table {
		compatible = "operating-points-v2";

		opp-125000000 {
			opp-hz = /bits/ 64 <125000000>;
			opp-microvolt = <950000>;
		};
		opp-250000000 {
			opp-hz = /bits/ 64 <250000000>;
			opp-microvolt = <950000>;
		};
		opp-285714285 {
			opp-hz = /bits/ 64 <285714285>;
			opp-microvolt = <950000>;
		};
		opp-400000000 {
			opp-hz = /bits/ 64 <400000000>;
			opp-microvolt = <950000>;
		};
		opp-500000000 {
			opp-hz = /bits/ 64 <500000000>;
			opp-microvolt = <950000>;
		};
		opp-666666666 {
			opp-hz = /bits/ 64 <666666666>;
			opp-microvolt = <950000>;
		};
		opp-744000000 {
			opp-hz = /bits/ 64 <744000000>;
			opp-microvolt = <950000>;
		};
	};
};

&apb {
	mali: gpu@c0000 {
		compatible = "arm,mali-450";
		reg = <0x0 0xc0000 0x0 0x40000>;
		interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "gp", "gpmmu", "pp", "pmu",
			"pp0", "ppmmu0", "pp1", "ppmmu1",
			"pp2", "ppmmu2";
		operating-points-v2 = <&gpu_opp_table>;
	};
};
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