Commit 4a7514f7 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge branch 'lpc18xx_43xx_dts_4.3' of https://github.com/manabian/linux-lpc into next/dt 

Merge "LPC18xx DTS changes for 4.3" from Joachim Eastwood:

This patch set adds DT nodes for all the drivers that went upstream in
4.2 and should represent the bulk of DTS changes for 4.3.  All nodes
added are documented and some of patches carries a ack from subsystem
maintainer. It also features updates to the EA4357 dev- kit and a new
board from Ezequiel Garcia.

Note that there might be one more batch of DTS changes for 4.3 if any
new drivers goes upstream and also some changes for the Hitex eval board
might come.

* 'lpc18xx_43xx_dts_4.3' of https://github.com/manabian/linux-lpc

:
  ARM: dts: add DT for CIAA LPC4337 industrial computer
  of: add vendor prefix for CIAA project
  ARM: dts: lpc4357-ea4357: add uart3
  ARM: dts: lpc4357-ea4357: add ethernet
  ARM: dts: lpc4357-ea4357: add gpio joystick
  ARM: dts: lpc4357-ea4357: add mmcsd
  ARM: dts: lpc4357-ea4357: add pinctrl and uart0 muxing
  ARM: dts: lpc18xx: add usb nodes
  ARM: dts: lpc18xx: add ethernet node
  ARM: dts: lpc18xx: add creg (syscon) node
  ARM: dts: lpc18xx: add mmcsd node
  ARM: dts: lpc18xx: add can nodes
  ARM: dts: lpc18xx: add ssp nodes
  ARM: dts: lpc18xx: add gpio node
  ARM: dts: lpc18xx: add pinctrl node
  ARM: dts: lpc18xx: add uart new compat string and clk names
  ARM: dts: lpc18xx: add cgu and ccu clock-controller nodes

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents b1d725ee e794db2c

Documentation/devicetree/bindings/vendor-prefixes.txt

+1 −0
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ chipone ChipOne 
chipspark	ChipSPARK

chrp	Common Hardware Reference Platform

chunghwa	Chunghwa Picture Tubes Ltd.

ciaa	Computadora Industrial Abierta Argentina

cirrus	Cirrus Logic, Inc.

cloudengines	Cloud Engines, Inc.

cnm	Chips&Media, Inc.

arch/arm/boot/dts/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -211,6 +211,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \ 
	kirkwood-ts419-6281.dtb \

	kirkwood-ts419-6282.dtb

dtb-$(CONFIG_ARCH_LPC18XX) += \

	lpc4337-ciaa.dtb \

	lpc4350-hitex-eval.dtb \

	lpc4357-ea4357-devkit.dtb

dtb-$(CONFIG_ARCH_LPC32XX) += \

arch/arm/boot/dts/lpc18xx.dtsi

+217 −18
Original line number Diff line number Diff line
@@ -13,6 +13,12 @@ 


#include "armv7-m.dtsi"



#include "dt-bindings/clock/lpc18xx-cgu.h"

#include "dt-bindings/clock/lpc18xx-ccu.h"



#define LPC_PIN(port, pin)	(0x##port * 32 + pin)

#define LPC_GPIO(port, pin)	(port * 32 + pin)



/ {

	cpus {

		#address-cells = <1>;
@@ -22,6 +28,7 @@ 
			compatible = "arm,cortex-m3";

			device_type = "cpu";

			reg = <0x0>;

			clocks = <&ccu1 CLK_CPU_CORE>;

		};

	};
@@ -32,32 +39,141 @@ 
			clock-frequency = <12000000>;

		};



		/* Temporary hardcode PLL1 until clk drivers are merged */

		pll1: pll1 {

			compatible = "fixed-factor-clock";

			clocks = <&xtal>;

		xtal32: xtal32 {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <32768>;

		};



		enet_rx_clk: enet_rx_clk {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <0>;

			clock-output-names = "enet_rx_clk";

		};



		enet_tx_clk: enet_tx_clk {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <0>;

			clock-output-names = "enet_tx_clk";

		};



		gp_clkin: gp_clkin {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-div = <1>;

			clock-mult = <12>;

			clock-frequency = <0>;

			clock-output-names = "gp_clkin";

		};

	};



	soc {

		mmcsd: mmcsd@40004000 {

			compatible = "snps,dw-mshc";

			reg = <0x40004000 0x1000>;

			interrupts = <6>;

			num-slots = <1>;

			clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>;

			clock-names = "ciu", "biu";

			status = "disabled";

		};



		usb0: ehci@40006100 {

			compatible = "nxp,lpc1850-ehci", "generic-ehci";

			reg = <0x40006100 0x100>;

			interrupts = <8>;

			clocks = <&ccu1 CLK_CPU_USB0>;

			has-transaction-translator;

			status = "disabled";

		};



		usb1: ehci@40007100 {

			compatible = "nxp,lpc1850-ehci", "generic-ehci";

			reg = <0x40007100 0x100>;

			interrupts = <9>;

			clocks = <&ccu1 CLK_CPU_USB1>;

			status = "disabled";

		};



		mac: ethernet@40010000 {

			compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac";

			reg = <0x40010000 0x2000>;

			interrupts = <5>;

			interrupt-names	= "macirq";

			clocks = <&ccu1 CLK_CPU_ETHERNET>;

			clock-names = "stmmaceth";

			status = "disabled";

		};



		creg: syscon@40043000 {

			compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";

			reg = <0x40043000 0x1000>;

			clocks = <&ccu1 CLK_CPU_CREG>;

		};



		cgu: clock-controller@40050000 {

			compatible = "nxp,lpc1850-cgu";

			reg = <0x40050000 0x1000>;

			#clock-cells = <1>;

			clocks = <&xtal>, <&xtal32>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;

		};



		ccu1: clock-controller@40051000 {

			compatible = "nxp,lpc1850-ccu";

			reg = <0x40051000 0x1000>;

			#clock-cells = <1>;

			clocks = <&cgu BASE_APB3_CLK>,   <&cgu BASE_APB1_CLK>,

				 <&cgu BASE_SPIFI_CLK>,  <&cgu BASE_CPU_CLK>,

				 <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,

				 <&cgu BASE_USB1_CLK>,   <&cgu BASE_SPI_CLK>;

			clock-names = "base_apb3_clk",   "base_apb1_clk",

				      "base_spifi_clk",  "base_cpu_clk",

				      "base_periph_clk", "base_usb0_clk",

				      "base_usb1_clk",   "base_spi_clk";

		};



		ccu2: clock-controller@40052000 {

			compatible = "nxp,lpc1850-ccu";

			reg = <0x40052000 0x1000>;

			#clock-cells = <1>;

			clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,

				 <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,

				 <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,

				 <&cgu BASE_SSP0_CLK>,  <&cgu BASE_SDIO_CLK>;

			clock-names = "base_audio_clk", "base_uart3_clk",

				      "base_uart2_clk", "base_uart1_clk",

				      "base_uart0_clk", "base_ssp1_clk",

				      "base_ssp0_clk",  "base_sdio_clk";

		};



		uart0: serial@40081000 {

			compatible = "ns16550a";

			compatible = "nxp,lpc1850-uart", "ns16550a";

			reg = <0x40081000 0x1000>;

			reg-shift = <2>;

			interrupts = <24>;

			clocks = <&pll1>;

			clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>;

			clock-names = "uartclk", "reg";

			status = "disabled";

		};



		uart1: serial@40082000 {

			compatible = "ns16550a";

			compatible = "nxp,lpc1850-uart", "ns16550a";

			reg = <0x40082000 0x1000>;

			reg-shift = <2>;

			interrupts = <25>;

			clocks = <&pll1>;

			clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;

			clock-names = "uartclk", "reg";

			status = "disabled";

		};



		ssp0: spi@40083000 {

			compatible = "arm,pl022", "arm,primecell";

			reg = <0x40083000 0x1000>;

			interrupts = <22>;

			clocks = <&ccu2 CLK_APB0_SSP0>, <&ccu1 CLK_CPU_SSP0>;

			clock-names = "sspclk", "apb_pclk";

			#address-cells = <1>;

			#size-cells = <0>;

			status = "disabled";

		};
@@ -65,7 +181,7 @@ 
			compatible = "nxp,lpc3220-timer";

			reg = <0x40084000 0x1000>;

			interrupts = <12>;

			clocks = <&pll1>;

			clocks = <&ccu1 CLK_CPU_TIMER0>;

			clock-names = "timerclk";

		};
@@ -73,25 +189,41 @@ 
			compatible = "nxp,lpc3220-timer";

			reg = <0x40085000 0x1000>;

			interrupts = <13>;

			clocks = <&pll1>;

			clocks = <&ccu1 CLK_CPU_TIMER1>;

			clock-names = "timerclk";

		};



		pinctrl: pinctrl@40086000 {

			compatible = "nxp,lpc1850-scu";

			reg = <0x40086000 0x1000>;

			clocks = <&ccu1 CLK_CPU_SCU>;

		};



		can1: can@400a4000 {

			compatible = "bosch,c_can";

			reg = <0x400a4000 0x1000>;

			interrupts = <43>;

			clocks = <&ccu1 CLK_APB1_CAN1>;

			status = "disabled";

		};



		uart2: serial@400c1000 {

			compatible = "ns16550a";

			compatible = "nxp,lpc1850-uart", "ns16550a";

			reg = <0x400c1000 0x1000>;

			reg-shift = <2>;

			interrupts = <26>;

			clocks = <&pll1>;

			clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>;

			clock-names = "uartclk", "reg";

			status = "disabled";

		};



		uart3: serial@400c2000 {

			compatible = "ns16550a";

			compatible = "nxp,lpc1850-uart", "ns16550a";

			reg = <0x400c2000 0x1000>;

			reg-shift = <2>;

			interrupts = <27>;

			clocks = <&pll1>;

			clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>;

			clock-names = "uartclk", "reg";

			status = "disabled";

		};
@@ -99,7 +231,7 @@ 
			compatible = "nxp,lpc3220-timer";

			reg = <0x400c3000 0x1000>;

			interrupts = <14>;

			clocks = <&pll1>;

			clocks = <&ccu1 CLK_CPU_TIMER2>;

			clock-names = "timerclk";

		};
@@ -107,8 +239,75 @@ 
			compatible = "nxp,lpc3220-timer";

			reg = <0x400c4000 0x1000>;

			interrupts = <15>;

			clocks = <&pll1>;

			clocks = <&ccu1 CLK_CPU_TIMER3>;

			clock-names = "timerclk";

		};



		ssp1: spi@400c5000 {

			compatible = "arm,pl022", "arm,primecell";

			reg = <0x400c5000 0x1000>;

			interrupts = <23>;

			clocks = <&ccu2 CLK_APB2_SSP1>, <&ccu1 CLK_CPU_SSP1>;

			clock-names = "sspclk", "apb_pclk";

			#address-cells = <1>;

			#size-cells = <0>;

			status = "disabled";

		};



		can0: can@400e2000 {

			compatible = "bosch,c_can";

			reg = <0x400e2000 0x1000>;

			interrupts = <51>;

			clocks = <&ccu1 CLK_APB3_CAN0>;

			status = "disabled";

		};



		gpio: gpio@400f4000 {

			compatible = "nxp,lpc1850-gpio";

			reg = <0x400f4000 0x4000>;

			clocks = <&ccu1 CLK_CPU_GPIO>;

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges =	<&pinctrl LPC_GPIO(0,0)  LPC_PIN(0,0)  2>,

					<&pinctrl LPC_GPIO(0,4)  LPC_PIN(1,0)  1>,

					<&pinctrl LPC_GPIO(0,8)  LPC_PIN(1,1)  4>,

					<&pinctrl LPC_GPIO(1,8)  LPC_PIN(1,5)  2>,

					<&pinctrl LPC_GPIO(1,0)  LPC_PIN(1,7)  8>,

					<&pinctrl LPC_GPIO(0,2)  LPC_PIN(1,15) 2>,

					<&pinctrl LPC_GPIO(0,12) LPC_PIN(1,17) 2>,

					<&pinctrl LPC_GPIO(0,15) LPC_PIN(1,20) 1>,

					<&pinctrl LPC_GPIO(5,0)  LPC_PIN(2,0)  7>,

					<&pinctrl LPC_GPIO(0,7)  LPC_PIN(2,7)  1>,

					<&pinctrl LPC_GPIO(5,7)  LPC_PIN(2,8)  1>,

					<&pinctrl LPC_GPIO(1,10) LPC_PIN(2,9)  1>,

					<&pinctrl LPC_GPIO(0,14) LPC_PIN(2,10) 1>,

					<&pinctrl LPC_GPIO(1,11) LPC_PIN(2,11) 3>,

					<&pinctrl LPC_GPIO(5,8)  LPC_PIN(3,1)  2>,

					<&pinctrl LPC_GPIO(1,14) LPC_PIN(3,4)  2>,

					<&pinctrl LPC_GPIO(0,6)  LPC_PIN(3,6)  1>,

					<&pinctrl LPC_GPIO(5,10) LPC_PIN(3,7)  2>,

					<&pinctrl LPC_GPIO(2,0)  LPC_PIN(4,0)  7>,

					<&pinctrl LPC_GPIO(5,12) LPC_PIN(4,8)  3>,

					<&pinctrl LPC_GPIO(2,9)  LPC_PIN(5,0)  7>,

					<&pinctrl LPC_GPIO(2,7)  LPC_PIN(5,7)  1>,

					<&pinctrl LPC_GPIO(3,0)  LPC_PIN(6,1)  5>,

					<&pinctrl LPC_GPIO(0,5)  LPC_PIN(6,6)  1>,

					<&pinctrl LPC_GPIO(5,15) LPC_PIN(6,7)  2>,

					<&pinctrl LPC_GPIO(3,5)  LPC_PIN(6,9)  3>,

					<&pinctrl LPC_GPIO(2,8)  LPC_PIN(6,12) 1>,

					<&pinctrl LPC_GPIO(3,8)  LPC_PIN(7,0)  8>,

					<&pinctrl LPC_GPIO(4,0)  LPC_PIN(8,0)  8>,

					<&pinctrl LPC_GPIO(4,12) LPC_PIN(9,0)  4>,

					<&pinctrl LPC_GPIO(5,17) LPC_PIN(9,4)  2>,

					<&pinctrl LPC_GPIO(4,11) LPC_PIN(9,6)  1>,

					<&pinctrl LPC_GPIO(4,8)  LPC_PIN(a,1)  3>,

					<&pinctrl LPC_GPIO(5,19) LPC_PIN(a,4)  1>,

					<&pinctrl LPC_GPIO(5,20) LPC_PIN(b,0)  7>,

					<&pinctrl LPC_GPIO(6,0)  LPC_PIN(c,1) 14>,

					<&pinctrl LPC_GPIO(6,14) LPC_PIN(d,0) 17>,

					<&pinctrl LPC_GPIO(7,0)  LPC_PIN(e,0) 16>,

					<&pinctrl LPC_GPIO(7,16) LPC_PIN(f,1)  3>,

					<&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5)  7>;

		};

	};

};

arch/arm/boot/dts/lpc4337-ciaa.dts

0 → 100644
+187 −0
Original line number Diff line number Diff line 
/*

 * CIAA NXP LPC4337 (http://www.proyecto-ciaa.com.ar)

 *

 * Copyright (C) 2015 VanguardiaSur - www.vanguardiasur.com.ar

 *

 * This code is released using a dual license strategy: BSD/GPL

 * You can choose the licence that better fits your requirements.

 *

 * Released under the terms of 3-clause BSD License

 * Released under the terms of GNU General Public License Version 2.0

 */

/dts-v1/;



#include "lpc18xx.dtsi"

#include "lpc4357.dtsi"



#include "dt-bindings/gpio/gpio.h"



/ {

	model = "CIAA NXP LPC4337";

	compatible = "ciaa,lpc4337", "nxp,lpc4337", "nxp,lpc4350";



	aliases {

		serial0 = &uart2;

		serial1 = &uart3;

	};



	chosen {

		bootargs = "console=ttyS0,115200 earlyprintk";

		stdout-path = &uart2;

	};



	memory {

		device_type = "memory";

		reg = <0x28000000 0x0800000>; /* 8 MB */

	};

};



&pinctrl {

	enet_rmii_pins: enet-rmii-pins {

		enet_rmii_rxd_cfg {

			pins = "p1_15", "p0_0";

			function = "enet";

			slew-rate = <1>;

			bias-disable;

			input-enable;

			input-schmitt-disable;

		};



		enet_rmii_txd_cfg {

			pins = "p1_18", "p1_20";

			function = "enet";

			slew-rate = <1>;

			bias-disable;

			input-enable;

			input-schmitt-disable;

		};



		enet_rmii_rx_dv_cfg {

			pins = "p1_16";

			function = "enet";

			bias-disable;

			input-enable;

			input-schmitt-disable;

		};



		enet_rmii_tx_en_cfg {

			pins = "p0_1";

			function = "enet";

			bias-disable;

			input-enable;

			input-schmitt-disable;

		};



		enet_ref_clk_cfg {

			pins = "p1_19";

			function = "enet";

			slew-rate = <1>;

			bias-disable;

			input-enable;

			input-schmitt-disable;

		};



		enet_mdio_cfg {

			pins = "p1_17";

			function = "enet";

			bias-disable;

			input-enable;

			input-schmitt-disable;

		};



		enet_mdc_cfg {

			pins = "p7_7";

			function = "enet";

			slew-rate = <1>;

			bias-disable;

			input-enable;

			input-schmitt-disable;

		};

	};



	ssp_pins: ssp-pins {

		ssp1_cs {

			pins = "p6_7";

			function = "gpio";

			bias-pull-up;

			bias-disable;

		};



		ssp1_miso_mosi {

			pins = "p1_3", "p1_4";

			function = "ssp1";

			slew-rate = <1>;

			bias-pull-down;

			input-enable;

			input-schmitt-disable;

		};



		ssp1_sck {

			pins = "pf_4";

			function = "ssp1";

			slew-rate = <1>;

			bias-disable;

		};

	};



	uart2_pins: uart2-pins {

		uart2_rx_cfg {

			pins = "p7_2";

			function = "uart2";

			bias-disable;

			input-enable;

		};



		uart2_tx_cfg {

			pins = "p7_1";

			function = "uart2";

			bias-disable;

		};

	};



	uart3_pins: uart3-pins {

		uart3_rx_cfg {

			pins = "p2_4";

			function = "uart3";

			bias-disable;

			input-enable;

		};



		uart3_tx_cfg {

			pins = "p2_3";

			function = "uart3";

			bias-disable;

		};

	};

};



&enet_tx_clk {

	clock-frequency = <50000000>;

};



&mac {

	status = "okay";

	phy-mode = "rmii";

	pinctrl-names = "default";

	pinctrl-0 = <&enet_rmii_pins>;

};



&ssp1 {

	status = "okay";

	pinctrl-names = "default";

	pinctrl-0 = <&ssp_pins>;

	cs-gpios = <&gpio LPC_GPIO(5,15) GPIO_ACTIVE_HIGH>;

	num-cs = <1>;

};



&uart2 {

	status = "okay";

	pinctrl-names = "default";

	pinctrl-0 = <&uart2_pins>;

};



&uart3 {

	status = "okay";

	pinctrl-names = "default";

	pinctrl-0 = <&uart3_pins>;

};

arch/arm/boot/dts/lpc4350-hitex-eval.dts

+0 −4
Original line number Diff line number Diff line
@@ -36,10 +36,6 @@ 
	};

};



&pll1 {

	clock-mult = <15>;

};



&uart0 {

	status = "okay";

};

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