Merge tag 'asoc-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus

 - reg:			The i2c address. Value depends on the state of ADDR0

			and ADDR1, as wired in hardware.

Optional properties:

 - clock-names:		If provided must be "mclk".

 - clocks:		phandle + clock-specifiers for the clock that provides

			the audio master clock for the device.

Examples:

#include <dt-bindings/sound/adau17x1.h>

		adau1361@38 {

			compatible = "adi,adau1761";

			reg = <0x38>;

			clock-names = "mclk";

			clocks = <&audio_clock>;

		};

	};

Analog Devices ADAU7002 Stereo PDM-to-I2S/TDM Converter

Required properties:

 - compatible: Must be "adi,adau7002"

Optional properties:

 - IOVDD-supply: Phandle and specifier for the power supply providing the IOVDD

	supply as covered in Documentation/devicetree/bindings/regulator/regulator.txt

	If this property is not present it is assumed that the supply pin is

	hardwired to always on.

Example:

	adau7002: pdm-to-i2s {

		compatible = "adi,adau7002";

		IOVDD-supply = <&supply>;

	};

BROADCOM Cygnus Audio I2S/TDM/SPDIF controller

Required properties:

	- compatible : "brcm,cygnus-audio"

	- #address-cells: 32bit valued, 1 cell.

	- #size-cells:  32bit valued, 0 cell.

	- reg : Should contain audio registers location and length

	- reg-names: names of the registers listed in "reg" property

		Valid names are "aud" and "i2s_in". "aud" contains a

		set of DMA, I2S_OUT and SPDIF registers. "i2s_in" contains

		a set of I2S_IN registers.

	- clocks: PLL and leaf clocks used by audio ports

	- assigned-clocks: PLL and leaf clocks

	- assigned-clock-parents: parent clocks of the assigned clocks

		(usually the PLL)

	- assigned-clock-rates: List of clock frequencies of the

		assigned clocks

	- clock-names: names of 3 leaf clocks used by audio ports

		Valid names are "ch0_audio", "ch1_audio", "ch2_audio"

	- interrupts: audio DMA interrupt number

SSP Subnode properties:

- reg: The index of ssp port interface to use

	Valid value are 0, 1, 2, or 3 (for spdif)

Example:

	cygnus_audio: audio@180ae000 {

		compatible = "brcm,cygnus-audio";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0x180ae000 0xafd>, <0x180aec00 0x1f8>;

		reg-names = "aud", "i2s_in";

		clocks = <&audiopll BCM_CYGNUS_AUDIOPLL_CH0>,

				<&audiopll BCM_CYGNUS_AUDIOPLL_CH1>,

				<&audiopll BCM_CYGNUS_AUDIOPLL_CH2>;

		assigned-clocks = <&audiopll BCM_CYGNUS_AUDIOPLL>,

							<&audiopll BCM_CYGNUS_AUDIOPLL_CH0>,

							<&audiopll BCM_CYGNUS_AUDIOPLL_CH1>,

							<&audiopll BCM_CYGNUS_AUDIOPLL_CH2>;

		assigned-clock-parents = <&audiopll BCM_CYGNUS_AUDIOPLL>;

		assigned-clock-rates = <1769470191>,

								<0>,

								<0>,

								<0>;

		clock-names = "ch0_audio", "ch1_audio", "ch2_audio";

		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;

		ssp0: ssp_port@0 {

			reg = <0>;

			status = "okay";

		};

		ssp1: ssp_port@1 {

			reg = <1>;

			status = "disabled";

		};

		ssp2: ssp_port@2 {

			reg = <2>;

			status = "disabled";

		};

		spdif: spdif_port@3 {

			reg = <3>;

			status = "disabled";

		};

	};

Required properties:

  - compatible : "delta,dfbmcs320"

  - compatible : "delta,dfbmcs320" or "linux,bt-sco"

Example:

CS35L33 Speaker Amplifier

Required properties:

  - compatible : "cirrus,cs35l33"

  - reg : the I2C address of the device for I2C

  - VA-supply, VP-supply : power supplies for the device,

    as covered in

    Documentation/devicetree/bindings/regulator/regulator.txt.

Optional properties:

  - reset-gpios : gpio used to reset the amplifier

  - interrupt-parent : Specifies the phandle of the interrupt controller to

    which the IRQs from CS35L33 are delivered to.

 -  interrupts : IRQ line info CS35L33.

    (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt

    for further information relating to interrupt properties)

  - cirrus,boost-ctl : Booster voltage use to supply the amp. If the value is

    0, then VBST = VP. If greater than 0, the boost voltage will be 3300mV with

    a value of 1 and will increase at a step size of 100mV until a maximum of

    8000mV.

  - cirrus,ramp-rate : On power up, it affects the time from when the power

    up sequence begins to the time the audio reaches a full-scale output.

    On power down, it affects the time from when the power-down sequence

    begins to when the amplifier disables the PWM outputs. If this property

    is not set then soft ramping will be disabled and ramp time would be

    20ms. If this property is set to 0,1,2,3 then ramp times would be 40ms,

    60ms,100ms,175ms respectively for 48KHz sample rate.

  - cirrus,boost-ipk : The maximum current allowed for the boost converter.

    The range starts at 1850000uA and goes to a maximum of 3600000uA

    with a step size of 15625uA. The default is 2500000uA.

  - cirrus,imon-adc-scale : Configures the scaling of data bits from the IMON

    ADC data word. This property can be set as a value of 0 for bits 15 down

    to 0, 6 for 21 down to 6, 7, for 22 down to 7, 8 for 23 down to 8.

Optional H/G Algorithm sub-node:

The cs35l33 node can have a single "cirrus,hg-algo" sub-node that will enable

the internal H/G Algorithm.

  - cirrus,hg-algo : Sub-node for internal Class H/G algorithm that

    controls the amplifier supplies.

Optional properties for the "cirrus,hg-algo" sub-node:

  - cirrus,mem-depth : Memory depth for the Class H/G algorithm measured in

    LRCLK cycles. If this property is set to 0, 1, 2, or 3 then the memory

    depths will be 1, 4, 8, 16 LRCLK cycles.  The default is 16 LRCLK cycles.

    cirrus,release-rate : The number of consecutive LRCLK periods before

    allowing release condition tracking updates. The number of LRCLK periods

    start at 3 to a maximum of 255.

  - cirrus,ldo-thld : Configures the signal threshold at which the PWM output

    stage enters LDO operation. Starts as a default value of 50mV for a value

    of 1 and increases with a step size of 50mV to a maximum of 750mV (value of

    0xF).

  - cirrus,ldo-path-disable : This is a boolean property. If present, the H/G

    algorithm uses the max detection path.  If not present, the LDO

    detection path is used.

  - cirrus,ldo-entry-delay : The LDO entry delay in milliseconds before the H/G

    algorithm switches to the LDO voltage.  This property can be set to values

    from 0 to 7 for delays of 5ms, 10ms, 50ms, 100ms, 200ms, 500ms, 1000ms.

    The default is 100ms.

  - cirrus,vp-hg-auto : This is a boolean property.  When set, class H/G VPhg

    automatic updating is enabled.

  - cirrus,vp-hg :  Class H/G algorithm VPhg.  Controls the H/G algorithm's

    reference to the VP voltage for when to start generating a boosted VBST.

    The reference voltage starts at 3000mV with a value of 0x3 and is increased

    by 100mV per step to a maximum of 5500mV.

  - cirrus,vp-hg-rate : The rate (number of LRCLK periods) at which the VPhg is

    allowed to increase to a higher voltage when using VPhg automatic

    tracking. This property can be set to values from 0 to 3 with rates of 128

    periods, 2048 periods, 32768 periods, and 524288 periods.

    The default is 32768 periods.

  - cirrus,vp-hg-va : VA calculation reference for automatic VPhg tracking

    using VPMON. This property can be set to values from 0 to 6 starting at

    1800mV with a step size of 50mV up to a maximum value of 1750mV.

    Default is 1800mV.

Example:

cs35l33: cs35l33@40 {

	compatible = "cirrus,cs35l33";

	reg = <0x40>;

	VA-supply = <&ldo5_reg>;

	VP-supply = <&ldo5_reg>;

	interrupt-parent = <&gpio8>;

	interrupts = <3 IRQ_TYPE_LEVEL_LOW>;

	reset-gpios = <&cs47l91 34 0>;

	cirrus,ramp-rate = <0x0>;

	cirrus,boost-ctl = <0x30>;  /* VBST = 8000mV */

	cirrus,boost-ipk = <0xE0>; /* 3600mA */

	cirrus,imon-adc-scale = <0> /* Bits 15 down to 0 */

	cirrus,hg-algo {

		cirrus,mem-depth = <0x3>;

		cirrus,release-rate = <0x3>;

		cirrus,ldo-thld = <0x1>;

		cirrus,ldo-path-disable = <0x0>;

		cirrus,ldo-entry-delay=<0x4>;

		cirrus,vp-hg-auto;

		cirrus,vp-hg=<0xF>;

		cirrus,vp-hg-rate=<0x2>;

		cirrus,vp-hg-va=<0x0>;

	};

};