Commit 4a5861f7 authored Feb 15, 2019 by Rajat Jain Committed by Darren Hart (VMware) Feb 23, 2019

platform/x86: intel_pmc_core: Avoid a u32 overflow



The register (SLP_S0_RES) at offset slp_s0_offset is a 32 bit register.
The pmc_core_adjust_slp_s0_step() could overflow the u32 value while
returning it after adjusting the step. Thus change to u64, this is
already accounted for in debugfs attribute (that wants to output a
64 bit value).

Signed-off-by: Rajat Jain <rajatja@google.com>
Acked-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>

parent f27e1d18

drivers/platform/x86/intel_pmc_core.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -330,9 +330,9 @@ static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int
		writel(val, pmcdev->regbase + reg_offset);
		}

		static inline u32 pmc_core_adjust_slp_s0_step(u32 value)
		static inline u64 pmc_core_adjust_slp_s0_step(u32 value)
		{
		return value * SPT_PMC_SLP_S0_RES_COUNTER_STEP;
		return (u64)value * SPT_PMC_SLP_S0_RES_COUNTER_STEP;
		}

		static int pmc_core_dev_state_get(void data, u64 val)

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