powerpc/book3s/32: Use MMU_FTR_HPTE_TABLE in head_32.S (4a3a224c) · Commits · 戴 / test

arch/powerpc/kernel/head_32.S

+4 −0

Original line number	Diff line number	Diff line
		@@ -393,7 +393,9 @@ DataAccess:
		bne 1f /* if not, try to put a PTE */
		mfspr r4,SPRN_DAR /* into the hash table */
		rlwinm r3,r10,32-15,21,21 /* DSISR_STORE -> _PAGE_RW */
		BEGIN_MMU_FTR_SECTION
		bl hash_page
		END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
		1: lwz r5,_DSISR(r11) /* get DSISR value */
		mfspr r4,SPRN_DAR
		EXC_XFER_LITE(0x300, handle_page_fault)
		@@ -408,7 +410,9 @@ InstructionAccess:
		beq 1f /* if so, try to put a PTE */
		li r3,0 /* into the hash table */
		mr r4,r12 /* SRR0 is fault address */
		BEGIN_MMU_FTR_SECTION
		bl hash_page
		END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
		1: mr r4,r12
		andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */
		EXC_XFER_LITE(0x400, handle_page_fault)

+1 −11

Original line number	Diff line number	Diff line
		@@ -184,20 +184,10 @@ void __init MMU_init_hw(void)

		extern unsigned int hash_page_patch_A[];
		extern unsigned int hash_page_patch_B[], hash_page_patch_C[];
		extern unsigned int hash_page[];
		extern unsigned int flush_hash_patch_A[], flush_hash_patch_B[];

		if (!mmu_has_feature(MMU_FTR_HPTE_TABLE)) {
		/*
		* Put a blr (procedure return) instruction at the
		* start of hash_page, since we can still get DSI
		* exceptions on a 603.
		*/
		hash_page[0] = 0x4e800020;
		flush_icache_range((unsigned long) &hash_page[0],
		(unsigned long) &hash_page[1]);
		if (!mmu_has_feature(MMU_FTR_HPTE_TABLE))
		return;
		}

		if ( ppc_md.progress ) ppc_md.progress("hash:enter", 0x105);