Commit 4a31c08d authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6 

* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (26 commits)
  sh: Convert sh to use read/update_persistent_clock
  sh: Move PMB debugfs entry initialization to later stage
  sh: Fix up flush_cache_vmap() on SMP.
  sh: fix up MMU reset with variable PMB mapping sizes.
  sh: establish PMB mappings for NUMA nodes.
  sh: check for existing mappings for bolted PMB entries.
  sh: fixed virt/phys mapping helpers for PMB.
  sh: make pmb iomapping configurable.
  sh: reworked dynamic PMB mapping.
  sh: Fix up cpumask_of_pcibus() for the NUMA build.
  serial: sh-sci: Tidy up build warnings.
  sh: Fix up ctrl_read/write stragglers in migor setup.
  serial: sh-sci: Add DMA support.
  dmaengine: shdma: extend .device_terminate_all() to record partial transfer
  sh: merge sh7722 and sh7724 DMA register definitions
  sh: activate runtime PM for dmaengine on sh7722 and sh7724
  dmaengine: shdma: add runtime PM support.
  dmaengine: shdma: separate DMA headers.
  dmaengine: shdma: convert to platform device resources
  dmaengine: shdma: fix DMA error handling.
  ...
parents 2ddb3b15 0272282f

arch/sh/boards/mach-migor/setup.c

+16 −0
Original line number Diff line number Diff line
@@ -419,6 +419,9 @@ static struct i2c_board_info migor_i2c_devices[] = { 
		I2C_BOARD_INFO("migor_ts", 0x51),

		.irq = 38, /* IRQ6 */

	},

	{

		I2C_BOARD_INFO("wm8978", 0x1a),

	},

};



static struct i2c_board_info migor_i2c_camera[] = {
@@ -619,6 +622,19 @@ static int __init migor_devices_setup(void) 


	platform_resource_setup_memory(&migor_ceu_device, "ceu", 4 << 20);



	/* SIU: Port B */

	gpio_request(GPIO_FN_SIUBOLR, NULL);

	gpio_request(GPIO_FN_SIUBOBT, NULL);

	gpio_request(GPIO_FN_SIUBISLD, NULL);

	gpio_request(GPIO_FN_SIUBOSLD, NULL);

	gpio_request(GPIO_FN_SIUMCKB, NULL);



	/*

	 * The original driver sets SIUB OLR/OBT, ILR/IBT, and SIUA OLR/OBT to

	 * output. Need only SIUB, set to output for master mode (table 34.2)

	 */

	__raw_writew(__raw_readw(PORT_MSELCRA) | 1, PORT_MSELCRA);



	i2c_register_board_info(0, migor_i2c_devices,

				ARRAY_SIZE(migor_i2c_devices));

arch/sh/include/asm/cacheflush.h

+2 −2
Original line number Diff line number Diff line
@@ -86,8 +86,8 @@ extern void copy_from_user_page(struct vm_area_struct *vma, 
	struct page *page, unsigned long vaddr, void *dst, const void *src,

	unsigned long len);



#define flush_cache_vmap(start, end)		flush_cache_all()

#define flush_cache_vunmap(start, end)		flush_cache_all()

#define flush_cache_vmap(start, end)		local_flush_cache_all(NULL)

#define flush_cache_vunmap(start, end)		local_flush_cache_all(NULL)



#define flush_dcache_mmap_lock(mapping)		do { } while (0)

#define flush_dcache_mmap_unlock(mapping)	do { } while (0)

arch/sh/include/asm/dma-register.h

0 → 100644
+51 −0
Original line number Diff line number Diff line 
/*

 * Common header for the legacy SH DMA driver and the new dmaengine driver

 *

 * extracted from arch/sh/include/asm/dma-sh.h:

 *

 * Copyright (C) 2000  Takashi YOSHII

 * Copyright (C) 2003  Paul Mundt

 *

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 */

#ifndef DMA_REGISTER_H

#define DMA_REGISTER_H



/* DMA register */

#define SAR	0x00

#define DAR	0x04

#define TCR	0x08

#define CHCR	0x0C

#define DMAOR	0x40



/* DMAOR definitions */

#define DMAOR_AE	0x00000004

#define DMAOR_NMIF	0x00000002

#define DMAOR_DME	0x00000001



/* Definitions for the SuperH DMAC */

#define REQ_L	0x00000000

#define REQ_E	0x00080000

#define RACK_H	0x00000000

#define RACK_L	0x00040000

#define ACK_R	0x00000000

#define ACK_W	0x00020000

#define ACK_H	0x00000000

#define ACK_L	0x00010000

#define DM_INC	0x00004000

#define DM_DEC	0x00008000

#define DM_FIX	0x0000c000

#define SM_INC	0x00001000

#define SM_DEC	0x00002000

#define SM_FIX	0x00003000

#define RS_IN	0x00000200

#define RS_OUT	0x00000300

#define TS_BLK	0x00000040

#define TM_BUR	0x00000020

#define CHCR_DE	0x00000001

#define CHCR_TE	0x00000002

#define CHCR_IE	0x00000004



#endif

arch/sh/include/asm/dma-sh.h

+2 −86
Original line number Diff line number Diff line
@@ -11,7 +11,8 @@ 
#ifndef __DMA_SH_H

#define __DMA_SH_H



#include <asm/dma.h>

#include <asm/dma-register.h>

#include <cpu/dma-register.h>

#include <cpu/dma.h>



/* DMAOR contorl: The DMAOR access size is different by CPU.*/
@@ -53,34 +54,6 @@ static int dmte_irq_map[] __maybe_unused = { 
#endif

};



/* Definitions for the SuperH DMAC */

#define REQ_L	0x00000000

#define REQ_E	0x00080000

#define RACK_H	0x00000000

#define RACK_L	0x00040000

#define ACK_R	0x00000000

#define ACK_W	0x00020000

#define ACK_H	0x00000000

#define ACK_L	0x00010000

#define DM_INC	0x00004000

#define DM_DEC	0x00008000

#define DM_FIX	0x0000c000

#define SM_INC	0x00001000

#define SM_DEC	0x00002000

#define SM_FIX	0x00003000

#define RS_IN	0x00000200

#define RS_OUT	0x00000300

#define TS_BLK	0x00000040

#define TM_BUR	0x00000020

#define CHCR_DE 0x00000001

#define CHCR_TE 0x00000002

#define CHCR_IE 0x00000004



/* DMAOR definitions */

#define DMAOR_AE	0x00000004

#define DMAOR_NMIF	0x00000002

#define DMAOR_DME	0x00000001



/*

 * Define the default configuration for dual address memory-memory transfer.

 * The 0x400 value represents auto-request, external->external.
@@ -111,61 +84,4 @@ static u32 dma_base_addr[] __maybe_unused = { 
#endif

};



/* DMA register */

#define SAR     0x00

#define DAR     0x04

#define TCR     0x08

#define CHCR    0x0C

#define DMAOR	0x40



/*

 * for dma engine

 *

 * SuperH DMA mode

 */

#define SHDMA_MIX_IRQ	(1 << 1)

#define SHDMA_DMAOR1	(1 << 2)

#define SHDMA_DMAE1	(1 << 3)



enum sh_dmae_slave_chan_id {

	SHDMA_SLAVE_SCIF0_TX,

	SHDMA_SLAVE_SCIF0_RX,

	SHDMA_SLAVE_SCIF1_TX,

	SHDMA_SLAVE_SCIF1_RX,

	SHDMA_SLAVE_SCIF2_TX,

	SHDMA_SLAVE_SCIF2_RX,

	SHDMA_SLAVE_SCIF3_TX,

	SHDMA_SLAVE_SCIF3_RX,

	SHDMA_SLAVE_SCIF4_TX,

	SHDMA_SLAVE_SCIF4_RX,

	SHDMA_SLAVE_SCIF5_TX,

	SHDMA_SLAVE_SCIF5_RX,

	SHDMA_SLAVE_SIUA_TX,

	SHDMA_SLAVE_SIUA_RX,

	SHDMA_SLAVE_SIUB_TX,

	SHDMA_SLAVE_SIUB_RX,

	SHDMA_SLAVE_NUMBER,	/* Must stay last */

};



struct sh_dmae_slave_config {

	enum sh_dmae_slave_chan_id	slave_id;

	dma_addr_t			addr;

	u32				chcr;

	char				mid_rid;

};



struct sh_dmae_pdata {

	unsigned int mode;

	struct sh_dmae_slave_config *config;

	int config_num;

};



struct device;



struct sh_dmae_slave {

	enum sh_dmae_slave_chan_id	slave_id; /* Set by the platform */

	struct device			*dma_dev; /* Set by the platform */

	struct sh_dmae_slave_config	*config;  /* Set by the driver */

};



#endif /* __DMA_SH_H */

arch/sh/include/asm/dmaengine.h

0 → 100644
+93 −0
Original line number Diff line number Diff line 
/*

 * Header for the new SH dmaengine driver

 *

 * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */

#ifndef ASM_DMAENGINE_H

#define ASM_DMAENGINE_H



#include <linux/dmaengine.h>

#include <linux/list.h>



#include <asm/dma-register.h>



#define SH_DMAC_MAX_CHANNELS	6



enum sh_dmae_slave_chan_id {

	SHDMA_SLAVE_SCIF0_TX,

	SHDMA_SLAVE_SCIF0_RX,

	SHDMA_SLAVE_SCIF1_TX,

	SHDMA_SLAVE_SCIF1_RX,

	SHDMA_SLAVE_SCIF2_TX,

	SHDMA_SLAVE_SCIF2_RX,

	SHDMA_SLAVE_SCIF3_TX,

	SHDMA_SLAVE_SCIF3_RX,

	SHDMA_SLAVE_SCIF4_TX,

	SHDMA_SLAVE_SCIF4_RX,

	SHDMA_SLAVE_SCIF5_TX,

	SHDMA_SLAVE_SCIF5_RX,

	SHDMA_SLAVE_SIUA_TX,

	SHDMA_SLAVE_SIUA_RX,

	SHDMA_SLAVE_SIUB_TX,

	SHDMA_SLAVE_SIUB_RX,

	SHDMA_SLAVE_NUMBER,	/* Must stay last */

};



struct sh_dmae_slave_config {

	enum sh_dmae_slave_chan_id	slave_id;

	dma_addr_t			addr;

	u32				chcr;

	char				mid_rid;

};



struct sh_dmae_channel {

	unsigned int	offset;

	unsigned int	dmars;

	unsigned int	dmars_bit;

};



struct sh_dmae_pdata {

	struct sh_dmae_slave_config *slave;

	int slave_num;

	struct sh_dmae_channel *channel;

	int channel_num;

	unsigned int ts_low_shift;

	unsigned int ts_low_mask;

	unsigned int ts_high_shift;

	unsigned int ts_high_mask;

	unsigned int *ts_shift;

	int ts_shift_num;

	u16 dmaor_init;

};



struct device;



/* Used by slave DMA clients to request DMA to/from a specific peripheral */

struct sh_dmae_slave {

	enum sh_dmae_slave_chan_id	slave_id; /* Set by the platform */

	struct device			*dma_dev; /* Set by the platform */

	struct sh_dmae_slave_config	*config;  /* Set by the driver */

};



struct sh_dmae_regs {

	u32 sar; /* SAR / source address */

	u32 dar; /* DAR / destination address */

	u32 tcr; /* TCR / transfer count */

};



struct sh_desc {

	struct sh_dmae_regs hw;

	struct list_head node;

	struct dma_async_tx_descriptor async_tx;

	enum dma_data_direction direction;

	dma_cookie_t cookie;

	size_t partial;

	int chunks;

	int mark;

};



#endif

CRA Git | Maintained and supported by SUSTech CRA and CCSE