iommu/vt-d: Update register definitions to VT-d 3.0 specification

#define	DMAR_PEDATA_REG	0xe4	/* Page request event interrupt data register */

#define	DMAR_PEADDR_REG	0xe8	/* Page request event interrupt addr register */

#define	DMAR_PEUADDR_REG 0xec	/* Page request event Upper address register */

#define DMAR_MTRRCAP_REG 0x100	/* MTRR capability register */

#define DMAR_MTRRDEF_REG 0x108	/* MTRR default type register */

#define DMAR_MTRR_FIX64K_00000_REG 0x120 /* MTRR Fixed range registers */

#define DMAR_MTRR_FIX16K_80000_REG 0x128

#define DMAR_MTRR_FIX16K_A0000_REG 0x130

#define DMAR_MTRR_FIX4K_C0000_REG 0x138

#define DMAR_MTRR_FIX4K_C8000_REG 0x140

#define DMAR_MTRR_FIX4K_D0000_REG 0x148

#define DMAR_MTRR_FIX4K_D8000_REG 0x150

#define DMAR_MTRR_FIX4K_E0000_REG 0x158

#define DMAR_MTRR_FIX4K_E8000_REG 0x160

#define DMAR_MTRR_FIX4K_F0000_REG 0x168

#define DMAR_MTRR_FIX4K_F8000_REG 0x170

#define DMAR_MTRR_PHYSBASE0_REG 0x180 /* MTRR Variable range registers */

#define DMAR_MTRR_PHYSMASK0_REG 0x188

#define DMAR_MTRR_PHYSBASE1_REG 0x190

#define DMAR_MTRR_PHYSMASK1_REG 0x198

#define DMAR_MTRR_PHYSBASE2_REG 0x1a0

#define DMAR_MTRR_PHYSMASK2_REG 0x1a8

#define DMAR_MTRR_PHYSBASE3_REG 0x1b0

#define DMAR_MTRR_PHYSMASK3_REG 0x1b8

#define DMAR_MTRR_PHYSBASE4_REG 0x1c0

#define DMAR_MTRR_PHYSMASK4_REG 0x1c8

#define DMAR_MTRR_PHYSBASE5_REG 0x1d0

#define DMAR_MTRR_PHYSMASK5_REG 0x1d8

#define DMAR_MTRR_PHYSBASE6_REG 0x1e0

#define DMAR_MTRR_PHYSMASK6_REG 0x1e8

#define DMAR_MTRR_PHYSBASE7_REG 0x1f0

#define DMAR_MTRR_PHYSMASK7_REG 0x1f8

#define DMAR_MTRR_PHYSBASE8_REG 0x200

#define DMAR_MTRR_PHYSMASK8_REG 0x208

#define DMAR_MTRR_PHYSBASE9_REG 0x210

#define DMAR_MTRR_PHYSMASK9_REG 0x218

#define DMAR_VCCAP_REG		0xe00 /* Virtual command capability register */

#define DMAR_VCMD_REG		0xe10 /* Virtual command register */

#define DMAR_VCRSP_REG		0xe20 /* Virtual command response register */

#define OFFSET_STRIDE		(9)