Commit 4a1c93cb authored by Will Deacon's avatar Will Deacon
Browse files

iommu/arm-smmu: ensure CBA2R is initialised before CBAR on SMMUv2 



The VMID16 (8.1) extension to SMMUv2 added a 16-bit VMID16 field to the
CBA2R registers. Unfortunately, if software writes this field as zero
after setting an 8-bit VMID in a stage-2 CBAR, then the VMID may also be
overwritten with zero on some early implementations (the architecture
was later updated to fix this issue).

This patch ensures that we initialise CBA2R before CBAR, therefore
ensuring that the VMID is set correctly.

Tested-by: default avatarManish Jaggi <mjaggi@caviumnetworks.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 06e5801b

drivers/iommu/arm-smmu.c

+14 −10
Original line number Original line Diff line number Diff line
@@ -730,6 +730,20 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, 
	stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;

	stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;

	cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);

	cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);





	if (smmu->version > ARM_SMMU_V1) {

		/*

		 * CBA2R.

		 * *Must* be initialised before CBAR thanks to VMID16

		 * architectural oversight affected some implementations.

		 */

#ifdef CONFIG_64BIT

		reg = CBA2R_RW64_64BIT;

#else

		reg = CBA2R_RW64_32BIT;

#endif

		writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx));

	}



	/* CBAR */

	/* CBAR */

	reg = cfg->cbar;

	reg = cfg->cbar;

	if (smmu->version == ARM_SMMU_V1)

	if (smmu->version == ARM_SMMU_V1)
@@ -747,16 +761,6 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, 
	}

	}

	writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx));

	writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx));





	if (smmu->version > ARM_SMMU_V1) {

		/* CBA2R */

#ifdef CONFIG_64BIT

		reg = CBA2R_RW64_64BIT;

#else

		reg = CBA2R_RW64_32BIT;

#endif

		writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx));

	}



	/* TTBRs */

	/* TTBRs */

	if (stage1) {

	if (stage1) {

		reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0];

		reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0];

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