Commit 4a1c2c7f authored by Marc Zyngier's avatar Marc Zyngier
Browse files

KVM: arm64: Fix AArch32 handling of DBGD{CCINT,SCRext} and DBGVCR 



The DBGD{CCINT,SCRext} and DBGVCR register entries in the cp14 array
are missing their target register, resulting in all accesses being
targetted at the guard sysreg (indexed by __INVALID_SYSREG__).

Point the emulation code at the actual register entries.

Fixes: bdfb4b38 ("arm64: KVM: add trap handlers for AArch32 debug registers")
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20201029172409.2768336-1-maz@kernel.org
parent 7efe8ef2

arch/arm64/include/asm/kvm_host.h

+1 −0
Original line number Diff line number Diff line
@@ -239,6 +239,7 @@ enum vcpu_sysreg { 
#define cp14_DBGWCR0	(DBGWCR0_EL1 * 2)

#define cp14_DBGWVR0	(DBGWVR0_EL1 * 2)

#define cp14_DBGDCCINT	(MDCCINT_EL1 * 2)

#define cp14_DBGVCR	(DBGVCR32_EL2 * 2)



#define NR_COPRO_REGS	(NR_SYS_REGS * 2)

arch/arm64/kvm/sys_regs.c

+3 −3
Original line number Diff line number Diff line
@@ -1881,9 +1881,9 @@ static const struct sys_reg_desc cp14_regs[] = { 
	{ Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },

	DBG_BCR_BVR_WCR_WVR(1),

	/* DBGDCCINT */

	{ Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32 },

	{ Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32, NULL, cp14_DBGDCCINT },

	/* DBGDSCRext */

	{ Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32 },

	{ Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32, NULL, cp14_DBGDSCRext },

	DBG_BCR_BVR_WCR_WVR(2),

	/* DBGDTR[RT]Xint */

	{ Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
@@ -1898,7 +1898,7 @@ static const struct sys_reg_desc cp14_regs[] = { 
	{ Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },

	DBG_BCR_BVR_WCR_WVR(6),

	/* DBGVCR */

	{ Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32 },

	{ Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32, NULL, cp14_DBGVCR },

	DBG_BCR_BVR_WCR_WVR(7),

	DBG_BCR_BVR_WCR_WVR(8),

	DBG_BCR_BVR_WCR_WVR(9),

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