Commit 49edbd49 authored by Madhav Chauhan's avatar Madhav Chauhan Committed by Jani Nikula
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drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers 



This patch defines TRANS_DDI_FUNC_CTL and TRANS_DDI_FUNC_CTL2
registers and their bitfields for DSI. These registers are used
for enabling port sync mode, input pipe select, data lane width
configuration etc.

v2: Changes:
    - Remove redundant extra line
    - Correct some of bitfield definition

v3 by Jani:
 - Move DSI transcoder offsets to GEN11_FEATURES

Signed-off-by: default avatarMadhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/6b2d87db82660320be10e423742cbf5a31e18037.1539613303.git.jani.nikula@intel.com
parent 9128b102

drivers/gpu/drm/i915/i915_pci.c

+3 −0
Original line number Diff line number Diff line
@@ -595,6 +595,9 @@ static const struct intel_device_info intel_cannonlake_info = { 


#define GEN11_FEATURES \

	GEN10_FEATURES, \

	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \

			   TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET, \

			   TRANSCODER_DSI0_OFFSET, TRANSCODER_DSI1_OFFSET}, \

	GEN(11), \

	.ddb_size = 2048, \

	.has_logical_ring_elsq = 1

drivers/gpu/drm/i915/i915_reg.h

+17 −0
Original line number Diff line number Diff line
@@ -4028,6 +4028,8 @@ enum { 
#define TRANSCODER_C_OFFSET 0x62000

#define CHV_TRANSCODER_C_OFFSET 0x63000

#define TRANSCODER_EDP_OFFSET 0x6f000

#define TRANSCODER_DSI0_OFFSET	0x6b000

#define TRANSCODER_DSI1_OFFSET	0x6b800



#define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \

	dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
@@ -8992,6 +8994,8 @@ enum skl_power_gate { 
#define _TRANS_DDI_FUNC_CTL_B		0x61400

#define _TRANS_DDI_FUNC_CTL_C		0x62400

#define _TRANS_DDI_FUNC_CTL_EDP		0x6F400

#define _TRANS_DDI_FUNC_CTL_DSI0	0x6b400

#define _TRANS_DDI_FUNC_CTL_DSI1	0x6bc00

#define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)



#define  TRANS_DDI_FUNC_ENABLE		(1 << 31)
@@ -9029,6 +9033,19 @@ enum skl_power_gate { 
					| TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \

					| TRANS_DDI_HDMI_SCRAMBLING)



#define _TRANS_DDI_FUNC_CTL2_A		0x60404

#define _TRANS_DDI_FUNC_CTL2_B		0x61404

#define _TRANS_DDI_FUNC_CTL2_C		0x62404

#define _TRANS_DDI_FUNC_CTL2_EDP	0x6f404

#define _TRANS_DDI_FUNC_CTL2_DSI0	0x6b404

#define _TRANS_DDI_FUNC_CTL2_DSI1	0x6bc04

#define TRANS_DDI_FUNC_CTL2(tran)	_MMIO_TRANS2(tran, \

						     _TRANS_DDI_FUNC_CTL2_A)

#define  PORT_SYNC_MODE_ENABLE			(1 << 4)

#define  PORT_SYNC_MODE_MASTER_SELECT(x)	((x) < 0)

#define  PORT_SYNC_MODE_MASTER_SELECT_MASK	(0x7 << 0)

#define  PORT_SYNC_MODE_MASTER_SELECT_SHIFT	0



/* DisplayPort Transport Control */

#define _DP_TP_CTL_A			0x64040

#define _DP_TP_CTL_B			0x64140

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