drm/i915: Make HAS_GMCH_DISPLAY only take dev_priv (49cff963) · Commits · 戴 / test

drivers/gpu/drm/i915/i915_drv.h

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -2859,7 +2859,7 @@ struct drm_i915_cmd_table {
	#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)		#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
	#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)		#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)

	#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->has_gmch_display)		#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)

	/* DPF == dynamic parity feature */		/* DPF == dynamic parity feature */
	#define HAS_L3_DPF(dev) (INTEL_INFO(dev)->has_l3_dpf)		#define HAS_L3_DPF(dev) (INTEL_INFO(dev)->has_l3_dpf)

drivers/gpu/drm/i915/intel_color.c

+3 −3

Original line number	Original line	Diff line number	Diff line
	@@ -273,7 +273,7 @@ static void i9xx_load_luts_internal(struct drm_crtc *crtc,
	enum pipe pipe = intel_crtc->pipe;		enum pipe pipe = intel_crtc->pipe;
	int i;		int i;

	if (HAS_GMCH_DISPLAY(dev)) {		if (HAS_GMCH_DISPLAY(dev_priv)) {
	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
	assert_dsi_pll_enabled(dev_priv);		assert_dsi_pll_enabled(dev_priv);
	else		else
	@@ -288,7 +288,7 @@ static void i9xx_load_luts_internal(struct drm_crtc *crtc,
	(drm_color_lut_extract(lut[i].green, 8) << 8) \|		(drm_color_lut_extract(lut[i].green, 8) << 8) \|
	drm_color_lut_extract(lut[i].blue, 8);		drm_color_lut_extract(lut[i].blue, 8);

	if (HAS_GMCH_DISPLAY(dev))		if (HAS_GMCH_DISPLAY(dev_priv))
	I915_WRITE(PALETTE(pipe, i), word);		I915_WRITE(PALETTE(pipe, i), word);
	else		else
	I915_WRITE(LGC_PALETTE(pipe, i), word);		I915_WRITE(LGC_PALETTE(pipe, i), word);
	@@ -297,7 +297,7 @@ static void i9xx_load_luts_internal(struct drm_crtc *crtc,
	for (i = 0; i < 256; i++) {		for (i = 0; i < 256; i++) {
	uint32_t word = (i << 16) \| (i << 8) \| i;		uint32_t word = (i << 16) \| (i << 8) \| i;

	if (HAS_GMCH_DISPLAY(dev))		if (HAS_GMCH_DISPLAY(dev_priv))
	I915_WRITE(PALETTE(pipe, i), word);		I915_WRITE(PALETTE(pipe, i), word);
	else		else
	I915_WRITE(LGC_PALETTE(pipe, i), word);		I915_WRITE(LGC_PALETTE(pipe, i), word);

drivers/gpu/drm/i915/intel_display.c

+4 −4

drivers/gpu/drm/i915/intel_dp.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -1583,7 +1583,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
	return ret;		return ret;
	}		}

	if (HAS_GMCH_DISPLAY(dev))		if (HAS_GMCH_DISPLAY(dev_priv))
	intel_gmch_panel_fitting(intel_crtc, pipe_config,		intel_gmch_panel_fitting(intel_crtc, pipe_config,
	intel_connector->panel.fitting_mode);		intel_connector->panel.fitting_mode);
	else		else

drivers/gpu/drm/i915/intel_dsi.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -1346,7 +1346,7 @@ static int intel_dsi_set_property(struct drm_connector *connector,
	DRM_DEBUG_KMS("no scaling not supported\n");		DRM_DEBUG_KMS("no scaling not supported\n");
	return -EINVAL;		return -EINVAL;
	}		}
	if (HAS_GMCH_DISPLAY(dev) &&		if (HAS_GMCH_DISPLAY(to_i915(dev)) &&
	val == DRM_MODE_SCALE_CENTER) {		val == DRM_MODE_SCALE_CENTER) {
	DRM_DEBUG_KMS("centering not supported\n");		DRM_DEBUG_KMS("centering not supported\n");
	return -EINVAL;		return -EINVAL;

Original line number	Original line	Diff line number	Diff line
	@@ -5034,7 +5034,7 @@ intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
	* event which is after the vblank start event, so we need to have a		* event which is after the vblank start event, so we need to have a
	* wait-for-vblank between disabling the plane and the pipe.		* wait-for-vblank between disabling the plane and the pipe.
	*/		*/
	if (HAS_GMCH_DISPLAY(dev)) {		if (HAS_GMCH_DISPLAY(dev_priv)) {
	intel_set_memory_cxsr(dev_priv, false);		intel_set_memory_cxsr(dev_priv, false);
	dev_priv->wm.vlv.cxsr = false;		dev_priv->wm.vlv.cxsr = false;
	intel_wait_for_vblank(dev, pipe);		intel_wait_for_vblank(dev, pipe);
	@@ -5099,7 +5099,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
	intel_pre_disable_primary(&crtc->base);		intel_pre_disable_primary(&crtc->base);
	}		}

	if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) {		if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev_priv)) {
	crtc->wm.cxsr_allowed = false;		crtc->wm.cxsr_allowed = false;

	/*		/*
	@@ -10893,7 +10893,7 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
	pos \|= y << CURSOR_Y_SHIFT;		pos \|= y << CURSOR_Y_SHIFT;

	/* ILK+ do this automagically */		/* ILK+ do this automagically */
	if (HAS_GMCH_DISPLAY(dev) &&		if (HAS_GMCH_DISPLAY(dev_priv) &&
	plane_state->base.rotation == DRM_ROTATE_180) {		plane_state->base.rotation == DRM_ROTATE_180) {
	base += (plane_state->base.crtc_h *		base += (plane_state->base.crtc_h *
	plane_state->base.crtc_w - 1) * 4;		plane_state->base.crtc_w - 1) * 4;
	@@ -16591,7 +16591,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
	if (crtc->active && !intel_crtc_has_encoders(crtc))		if (crtc->active && !intel_crtc_has_encoders(crtc))
	intel_crtc_disable_noatomic(&crtc->base);		intel_crtc_disable_noatomic(&crtc->base);

	if (crtc->active \|\| HAS_GMCH_DISPLAY(dev)) {		if (crtc->active \|\| HAS_GMCH_DISPLAY(dev_priv)) {
	/*		/*
	* We start out with underrun reporting disabled to avoid races.		* We start out with underrun reporting disabled to avoid races.
	* For correct bookkeeping mark this on active crtcs.		* For correct bookkeeping mark this on active crtcs.

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