Commit 498f2a4b authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'zynqmp-dt-for-v5.6' of https://github.com/Xilinx/linux-xlnx into arm/dt 

arm64: dts: zynqmp: DT changes for v5.6

- Switch from fixed to firmware based clock driver
- Wire power domain driver
- Wire all ina226 chips through IIO and IIO hwmon drivers
- Add missing dr_mode property to usb nodes
- Use gpio-line-names property instead of comments
- Use clock-output-names for si570 differentiation
- Minor DT fixes

* tag 'zynqmp-dt-for-v5.6' of https://github.com/Xilinx/linux-xlnx: (21 commits)
  arm64: zynqmp: Add label property to all ina226 on zcu106
  arm64: zynqmp: Enable iio-hwmon for ina226 on zcu106
  arm64: zynqmp: Add label property to all ina226 on zcu102
  arm64: zynqmp: Enable iio-hwmon for ina226 on zcu102
  arm64: zynqmp: Add label property to all ina226 on zcu111
  arm64: zynqmp: Enable iio-hwmon for ina226 on zcu111
  arm64: zynqmp: Enable iio-hwmon for ina226 on zcu100
  arm64: zynqmp: Setup default number of chipselects for zcu100
  arm64: zynqmp: Remove broken-cd from zcu100-revC
  arm64: zynqmp: Fix the si570 clock frequency on zcu111
  arm64: zynqmp: Setup clock-output-names for si570 chips
  arm64: zynqmp: Turn comment to gpio-line-names
  arm64: zynqmp: Fix address for tca6416_u97 chip on zcu104
  arm64: zynqmp: Remove addition number in node name
  arm64: zynqmp: Use ethernet-phy as node name for ethernet phys
  arm64: dts: xilinx: Add the power nodes for zynqmp
  arm64: dts: xilinx: Remove dtsi for fixed clock
  arm64: dts: xilinx: Add the clock nodes for zynqmp
  arm64: zynqmp: Add dr_mode property to usb node
  arm64: dts: zynqmp: Use decimal values for drm-clock properties
  ...

Link: https://lore.kernel.org/r/c70d2efa-9ee2-a764-5248-0e5bfbf29f8a@monstr.eu


Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents c14e723e 5a25e646

arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi

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// SPDX-License-Identifier: GPL-2.0+

/*

 * Clock specification for Xilinx ZynqMP

 *

 * (C) Copyright 2017 - 2019, Xilinx, Inc.

 *

 * Michal Simek <michal.simek@xilinx.com>

 */



#include <dt-bindings/clock/xlnx-zynqmp-clk.h>

/ {

	pss_ref_clk: pss_ref_clk {

		u-boot,dm-pre-reloc;

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <33333333>;

	};



	video_clk: video_clk {

		u-boot,dm-pre-reloc;

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <27000000>;

	};



	pss_alt_ref_clk: pss_alt_ref_clk {

		u-boot,dm-pre-reloc;

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <0>;

	};



	gt_crx_ref_clk: gt_crx_ref_clk {

		u-boot,dm-pre-reloc;

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <108000000>;

	};



	aux_ref_clk: aux_ref_clk {

		u-boot,dm-pre-reloc;

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <27000000>;

	};

};



&can0 {

	clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&can1 {

	clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&cpu0 {

	clocks = <&zynqmp_clk ACPU>;

};



&fpd_dma_chan1 {

	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&fpd_dma_chan2 {

	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&fpd_dma_chan3 {

	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&fpd_dma_chan4 {

	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&fpd_dma_chan5 {

	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&fpd_dma_chan6 {

	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&fpd_dma_chan7 {

	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&fpd_dma_chan8 {

	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&lpd_dma_chan1 {

	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&lpd_dma_chan2 {

	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&lpd_dma_chan3 {

	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&lpd_dma_chan4 {

	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&lpd_dma_chan5 {

	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&lpd_dma_chan6 {

	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&lpd_dma_chan7 {

	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&lpd_dma_chan8 {

	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&gem0 {

	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,

		 <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,

		 <&zynqmp_clk GEM_TSU>;

	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";

};



&gem1 {

	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,

		 <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,

		 <&zynqmp_clk GEM_TSU>;

	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";

};



&gem2 {

	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,

		 <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,

		 <&zynqmp_clk GEM_TSU>;

	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";

};



&gem3 {

	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,

		 <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,

		 <&zynqmp_clk GEM_TSU>;

	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";

};



&gpio {

	clocks = <&zynqmp_clk LPD_LSBUS>;

};



&i2c0 {

	clocks = <&zynqmp_clk I2C0_REF>;

};



&i2c1 {

	clocks = <&zynqmp_clk I2C1_REF>;

};



&pcie {

	clocks = <&zynqmp_clk PCIE_REF>;

};



&sata {

	clocks = <&zynqmp_clk SATA_REF>;

};



&sdhci0 {

	clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&sdhci1 {

	clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&spi0 {

	clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&spi1 {

	clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&ttc0 {

	clocks = <&zynqmp_clk LPD_LSBUS>;

};



&ttc1 {

	clocks = <&zynqmp_clk LPD_LSBUS>;

};



&ttc2 {

	clocks = <&zynqmp_clk LPD_LSBUS>;

};



&ttc3 {

	clocks = <&zynqmp_clk LPD_LSBUS>;

};



&uart0 {

	clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&uart1 {

	clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&usb0 {

	clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;

};



&usb1 {

	clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;

};



&watchdog0 {

	clocks = <&zynqmp_clk WDT>;

};

arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi

deleted100644 → 0
+0 −213
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// SPDX-License-Identifier: GPL-2.0+

/*

 * Clock specification for Xilinx ZynqMP

 *

 * (C) Copyright 2015 - 2018, Xilinx, Inc.

 *

 * Michal Simek <michal.simek@xilinx.com>

 */



/ {

	clk100: clk100 {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <100000000>;

	};



	clk125: clk125 {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <125000000>;

	};



	clk200: clk200 {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <200000000>;

	};



	clk250: clk250 {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <250000000>;

	};



	clk300: clk300 {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <300000000>;

	};



	clk600: clk600 {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <600000000>;

	};



	dp_aclk: clock0 {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <100000000>;

		clock-accuracy = <100>;

	};



	dp_aud_clk: clock1 {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <24576000>;

		clock-accuracy = <100>;

	};



	dpdma_clk: dpdma-clk {

		compatible = "fixed-clock";

		#clock-cells = <0x0>;

		clock-frequency = <533000000>;

	};



	drm_clock: drm-clock {

		compatible = "fixed-clock";

		#clock-cells = <0x0>;

		clock-frequency = <262750000>;

		clock-accuracy = <0x64>;

	};

};



&can0 {

	clocks = <&clk100 &clk100>;

};



&can1 {

	clocks = <&clk100 &clk100>;

};



&fpd_dma_chan1 {

	clocks = <&clk600>, <&clk100>;

};



&fpd_dma_chan2 {

	clocks = <&clk600>, <&clk100>;

};



&fpd_dma_chan3 {

	clocks = <&clk600>, <&clk100>;

};



&fpd_dma_chan4 {

	clocks = <&clk600>, <&clk100>;

};



&fpd_dma_chan5 {

	clocks = <&clk600>, <&clk100>;

};



&fpd_dma_chan6 {

	clocks = <&clk600>, <&clk100>;

};



&fpd_dma_chan7 {

	clocks = <&clk600>, <&clk100>;

};



&fpd_dma_chan8 {

	clocks = <&clk600>, <&clk100>;

};



&lpd_dma_chan1 {

	clocks = <&clk600>, <&clk100>;

};



&lpd_dma_chan2 {

	clocks = <&clk600>, <&clk100>;

};



&lpd_dma_chan3 {

	clocks = <&clk600>, <&clk100>;

};



&lpd_dma_chan4 {

	clocks = <&clk600>, <&clk100>;

};



&lpd_dma_chan5 {

	clocks = <&clk600>, <&clk100>;

};



&lpd_dma_chan6 {

	clocks = <&clk600>, <&clk100>;

};



&lpd_dma_chan7 {

	clocks = <&clk600>, <&clk100>;

};



&lpd_dma_chan8 {

	clocks = <&clk600>, <&clk100>;

};



&gem0 {

	clocks = <&clk125>, <&clk125>, <&clk125>;

};



&gem1 {

	clocks = <&clk125>, <&clk125>, <&clk125>;

};



&gem2 {

	clocks = <&clk125>, <&clk125>, <&clk125>;

};



&gem3 {

	clocks = <&clk125>, <&clk125>, <&clk125>;

};



&gpio {

	clocks = <&clk100>;

};



&i2c0 {

	clocks = <&clk100>;

};



&i2c1 {

	clocks = <&clk100>;

};



&sata {

	clocks = <&clk250>;

};



&sdhci0 {

	clocks = <&clk200 &clk200>;

};



&sdhci1 {

	clocks = <&clk200 &clk200>;

};



&spi0 {

	clocks = <&clk200 &clk200>;

};



&spi1 {

	clocks = <&clk200 &clk200>;

};



&uart0 {

	clocks = <&clk100 &clk100>;

};



&uart1 {

	clocks = <&clk100 &clk100>;

};



&usb0 {

	clocks = <&clk250>, <&clk250>;

};



&usb1 {

	clocks = <&clk250>, <&clk250>;

};



&watchdog0 {

	clocks = <&clk250>;

};

arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts

+2 −2
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
/*

 * dts file for Xilinx ZynqMP ZC1232

 *

 * (C) Copyright 2017 - 2018, Xilinx, Inc.

 * (C) Copyright 2017 - 2019, Xilinx, Inc.

 *

 * Michal Simek <michal.simek@xilinx.com>

 */
@@ -10,7 +10,7 @@ 
/dts-v1/;



#include "zynqmp.dtsi"

#include "zynqmp-clk.dtsi"

#include "zynqmp-clk-ccf.dtsi"



/ {

	model = "ZynqMP ZC1232 RevA";

arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts

+2 −2
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
/*

 * dts file for Xilinx ZynqMP ZC1254

 *

 * (C) Copyright 2015 - 2018, Xilinx, Inc.

 * (C) Copyright 2015 - 2019, Xilinx, Inc.

 *

 * Michal Simek <michal.simek@xilinx.com>

 * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
@@ -11,7 +11,7 @@ 
/dts-v1/;



#include "zynqmp.dtsi"

#include "zynqmp-clk.dtsi"

#include "zynqmp-clk-ccf.dtsi"



/ {

	model = "ZynqMP ZC1254 RevA";

arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts

+2 −2
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
/*

 * dts file for Xilinx ZynqMP ZC1275

 *

 * (C) Copyright 2017 - 2018, Xilinx, Inc.

 * (C) Copyright 2017 - 2019, Xilinx, Inc.

 *

 * Michal Simek <michal.simek@xilinx.com>

 * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
@@ -11,7 +11,7 @@ 
/dts-v1/;



#include "zynqmp.dtsi"

#include "zynqmp-clk.dtsi"

#include "zynqmp-clk-ccf.dtsi"



/ {

	model = "ZynqMP ZC1275 RevA";

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