Commit 496828e7 authored by Tom St Denis's avatar Tom St Denis Committed by Alex Deucher
Browse files

drm/amd/amdgpu: Add offset variant to SOC15 macros 



Allows reading/writing via SOC15 macros with offset for
various register banks.

Signed-off-by: default avatarTom St Denis <tom.stdenis@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9d90f0bd

drivers/gpu/drm/amd/amdgpu/soc15_common.h

+14 −0
Original line number Diff line number Diff line
@@ -63,6 +63,13 @@ struct nbio_pcie_index_data { 
		(3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \

		(ip##_BASE__INST##inst##_SEG4 + reg))))))



#define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \

	RREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \

		(1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \

		(2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \

		(3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \

		(ip##_BASE__INST##inst##_SEG4 + reg))))) + offset)



#define WREG32_SOC15(ip, inst, reg, value) \

	WREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \

		(1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
@@ -70,6 +77,13 @@ struct nbio_pcie_index_data { 
		(3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \

		(ip##_BASE__INST##inst##_SEG4 + reg))))), value)



#define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \

	WREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \

		(1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \

		(2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \

		(3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \

		(ip##_BASE__INST##inst##_SEG4 + reg))))) + offset, value)



#endif

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