Commit 494f8eb9 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'broadcom-iproc' 

Arun Parameswaran says:

====================
Add support for Broadcom's iProc MDIO and Cygnus Ethernet PHY

This patchset adds support for the iProc MDIO interface and the
Broadcom Cygnus SoC's internal Ethernet PHY.

The internal Ethernet PHY(s) in the Cygnus SoC's are accessed
via the MDIO interface found in most of the iProc based chips.

The patch also consolidates the common API's used by the
Broadcom phys to a common library. Existing Broadcom phy
drivers have been modified to use the common library API's.

This patch series is based on Linux v4.3-rc1 and is avaliable in:
https://github.com/Broadcom/cygnus-linux/tree/cygnus-net-phy-mdio-v3



The Ethernet driver for the iProc family will be submitted soon,
as will the device tree configurations for the different iProc
family SoCs.

Changes from v2:
- Modified drivers/net/phy/Kconfig to modify the BCM_CYGNUS_PHY
  driver to 'depends on MDIO_BCM_IPROC' instead of 'select'.
- Added github branch to the cover letter

Changes from v1:
- Updated device tree documentation for the iProc MDIO driver
  based on Florian's feedback.
- Moved the core register defines from the Cygnus PHY driver to
  'include/linux/brcmphy.h' based on Florian's feedback.
- Created a new patch/commit to modify the bcm7xxx phy driver
  to use the new core register defines.
- Modified the Kconfig entry for the Broadcom PHY library to
  'tristate' instead of 'bool'
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 91d2f14b 9200c27a

Documentation/devicetree/bindings/net/brcm,iproc-mdio.txt

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* Broadcom iProc MDIO bus controller



Required properties:

- compatible: should be "brcm,iproc-mdio"

- reg: address and length of the register set for the MDIO interface

- #size-cells: must be 1

- #address-cells: must be 0



Child nodes of this MDIO bus controller node are standard Ethernet PHY device

nodes as described in Documentation/devicetree/bindings/net/phy.txt



Example:



mdio@18002000 {

	compatible = "brcm,iproc-mdio";

	reg = <0x18002000 0x8>;

	#size-cells = <1>;

	#address-cells = <0>;



	enet-gphy@0 {

		reg = <0>;

	};

};

drivers/net/phy/Kconfig

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@@ -69,20 +69,39 @@ config SMSC_PHY 
	---help---

	  Currently supports the LAN83C185, LAN8187 and LAN8700 PHYs



config BCM_NET_PHYLIB

	tristate



config BROADCOM_PHY

	tristate "Drivers for Broadcom PHYs"

	select BCM_NET_PHYLIB

	---help---

	  Currently supports the BCM5411, BCM5421, BCM5461, BCM54616S, BCM5464,

	  BCM5481 and BCM5482 PHYs.



config BCM_CYGNUS_PHY

	tristate "Drivers for Broadcom Cygnus SoC internal PHY"

	depends on ARCH_BCM_CYGNUS || COMPILE_TEST

	depends on MDIO_BCM_IPROC

	select BCM_NET_PHYLIB

	---help---

	  This PHY driver is for the 1G internal PHYs of the Broadcom

	  Cygnus Family SoC.



	  Currently supports internal PHY's used in the BCM11300,

	  BCM11320, BCM11350, BCM11360, BCM58300, BCM58302,

	  BCM58303 & BCM58305 Broadcom Cygnus SoCs.



config BCM63XX_PHY

	tristate "Drivers for Broadcom 63xx SOCs internal PHY"

	depends on BCM63XX

	select BCM_NET_PHYLIB

	---help---

	  Currently supports the 6348 and 6358 PHYs.



config BCM7XXX_PHY

	tristate "Drivers for Broadcom 7xxx SOCs internal PHYs"

	select BCM_NET_PHYLIB

	---help---

	  Currently supports the BCM7366, BCM7439, BCM7445, and

	  40nm and 65nm generation of BCM7xxx Set Top Box SoCs.
@@ -225,6 +244,15 @@ config MDIO_BCM_UNIMAC 
	  This hardware can be found in the Broadcom GENET Ethernet MAC

	  controllers as well as some Broadcom Ethernet switches such as the

	  Starfighter 2 switches.



config MDIO_BCM_IPROC

	tristate "Broadcom iProc MDIO bus controller"

	depends on ARCH_BCM_IPROC || COMPILE_TEST

	depends on HAS_IOMEM && OF_MDIO

	help

	  This module provides a driver for the MDIO busses found in the

	  Broadcom iProc SoC's.



endif # PHYLIB



config MICREL_KS8995MA

drivers/net/phy/Makefile

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@@ -12,10 +12,12 @@ obj-$(CONFIG_QSEMI_PHY) += qsemi.o 
obj-$(CONFIG_SMSC_PHY)		+= smsc.o

obj-$(CONFIG_TERANETICS_PHY)	+= teranetics.o

obj-$(CONFIG_VITESSE_PHY)	+= vitesse.o

obj-$(CONFIG_BCM_NET_PHYLIB)	+= bcm-phy-lib.o

obj-$(CONFIG_BROADCOM_PHY)	+= broadcom.o

obj-$(CONFIG_BCM63XX_PHY)	+= bcm63xx.o

obj-$(CONFIG_BCM7XXX_PHY)	+= bcm7xxx.o

obj-$(CONFIG_BCM87XX_PHY)	+= bcm87xx.o

obj-$(CONFIG_BCM_CYGNUS_PHY)	+= bcm-cygnus.o

obj-$(CONFIG_ICPLUS_PHY)	+= icplus.o

obj-$(CONFIG_REALTEK_PHY)	+= realtek.o

obj-$(CONFIG_LSI_ET1011C_PHY)	+= et1011c.o
@@ -38,3 +40,4 @@ obj-$(CONFIG_MDIO_SUN4I) += mdio-sun4i.o 
obj-$(CONFIG_MDIO_MOXART)	+= mdio-moxart.o

obj-$(CONFIG_MDIO_BCM_UNIMAC)	+= mdio-bcm-unimac.o

obj-$(CONFIG_MICROCHIP_PHY)	+= microchip.o

obj-$(CONFIG_MDIO_BCM_IPROC)	+= mdio-bcm-iproc.o

drivers/net/phy/bcm-cygnus.c

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/*

 * Copyright (C) 2015 Broadcom Corporation

 *

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License as

 * published by the Free Software Foundation version 2.

 *

 * This program is distributed "as is" WITHOUT ANY WARRANTY of any

 * kind, whether express or implied; without even the implied warranty

 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

 * GNU General Public License for more details.

 */



/* Broadcom Cygnus SoC internal transceivers support. */

#include "bcm-phy-lib.h"

#include <linux/brcmphy.h>

#include <linux/module.h>

#include <linux/netdevice.h>

#include <linux/phy.h>



/* Broadcom Cygnus Phy specific registers */

#define MII_BCM_CYGNUS_AFE_VDAC_ICTRL_0  0x91E5 /* VDAL Control register */



static int bcm_cygnus_afe_config(struct phy_device *phydev)

{

	int rc;



	/* ensure smdspclk is enabled */

	rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, 0x0c30);

	if (rc < 0)

		return rc;



	/* AFE_VDAC_ICTRL_0 bit 7:4 Iq=1100 for 1g 10bt, normal modes */

	rc = bcm_phy_write_misc(phydev, 0x39, 0x01, 0xA7C8);

	if (rc < 0)

		return rc;



	/* AFE_HPF_TRIM_OTHERS bit11=1, short cascode enable for all modes*/

	rc = bcm_phy_write_misc(phydev, 0x3A, 0x00, 0x0803);

	if (rc < 0)

		return rc;



	/* AFE_TX_CONFIG_1 bit 7:4 Iq=1100 for test modes */

	rc = bcm_phy_write_misc(phydev, 0x3A, 0x01, 0xA740);

	if (rc < 0)

		return rc;



	/* AFE TEMPSEN_OTHERS rcal_HT, rcal_LT 10000 */

	rc = bcm_phy_write_misc(phydev, 0x3A, 0x03, 0x8400);

	if (rc < 0)

		return rc;



	/* AFE_FUTURE_RSV bit 2:0 rccal <2:0>=100 */

	rc = bcm_phy_write_misc(phydev, 0x3B, 0x00, 0x0004);

	if (rc < 0)

		return rc;



	/* Adjust bias current trim to overcome digital offSet */

	rc = phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x02);

	if (rc < 0)

		return rc;



	/* make rcal=100, since rdb default is 000 */

	rc = bcm_phy_write_exp(phydev, MII_BRCM_CORE_EXPB1, 0x10);

	if (rc < 0)

		return rc;



	/* CORE_EXPB0, Reset R_CAL/RC_CAL Engine */

	rc = bcm_phy_write_exp(phydev, MII_BRCM_CORE_EXPB0, 0x10);

	if (rc < 0)

		return rc;



	/* CORE_EXPB0, Disable Reset R_CAL/RC_CAL Engine */

	rc = bcm_phy_write_exp(phydev, MII_BRCM_CORE_EXPB0, 0x00);



	return 0;

}



static int bcm_cygnus_config_init(struct phy_device *phydev)

{

	int reg, rc;



	reg = phy_read(phydev, MII_BCM54XX_ECR);

	if (reg < 0)

		return reg;



	/* Mask interrupts globally. */

	reg |= MII_BCM54XX_ECR_IM;

	rc = phy_write(phydev, MII_BCM54XX_ECR, reg);

	if (rc)

		return rc;



	/* Unmask events of interest */

	reg = ~(MII_BCM54XX_INT_DUPLEX |

		MII_BCM54XX_INT_SPEED |

		MII_BCM54XX_INT_LINK);

	rc = phy_write(phydev, MII_BCM54XX_IMR, reg);

	if (rc)

		return rc;



	/* Apply AFE settings for the PHY */

	rc = bcm_cygnus_afe_config(phydev);

	if (rc)

		return rc;



	/* Advertise EEE */

	rc = bcm_phy_enable_eee(phydev);

	if (rc)

		return rc;



	/* Enable APD */

	return bcm_phy_enable_apd(phydev, false);

}



static int bcm_cygnus_resume(struct phy_device *phydev)

{

	int rc;



	genphy_resume(phydev);



	/* Re-initialize the PHY to apply AFE work-arounds and

	 * configurations when coming out of suspend.

	 */

	rc = bcm_cygnus_config_init(phydev);

	if (rc)

		return rc;



	/* restart auto negotiation with the new settings */

	return genphy_config_aneg(phydev);

}



static struct phy_driver bcm_cygnus_phy_driver[] = {

{

	.phy_id        = PHY_ID_BCM_CYGNUS,

	.phy_id_mask   = 0xfffffff0,

	.name          = "Broadcom Cygnus PHY",

	.features      = PHY_GBIT_FEATURES |

			SUPPORTED_Pause | SUPPORTED_Asym_Pause,

	.config_init   = bcm_cygnus_config_init,

	.config_aneg   = genphy_config_aneg,

	.read_status   = genphy_read_status,

	.ack_interrupt = bcm_phy_ack_intr,

	.config_intr   = bcm_phy_config_intr,

	.suspend       = genphy_suspend,

	.resume        = bcm_cygnus_resume,

} };



static struct mdio_device_id __maybe_unused bcm_cygnus_phy_tbl[] = {

	{ PHY_ID_BCM_CYGNUS, 0xfffffff0, },

	{ }

};

MODULE_DEVICE_TABLE(mdio, bcm_cygnus_phy_tbl);



module_phy_driver(bcm_cygnus_phy_driver);



MODULE_DESCRIPTION("Broadcom Cygnus internal PHY driver");

MODULE_LICENSE("GPL v2");

MODULE_AUTHOR("Broadcom Corporation");

drivers/net/phy/bcm-phy-lib.c

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/*

 * Copyright (C) 2015 Broadcom Corporation

 *

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License as

 * published by the Free Software Foundation version 2.

 *

 * This program is distributed "as is" WITHOUT ANY WARRANTY of any

 * kind, whether express or implied; without even the implied warranty

 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

 * GNU General Public License for more details.

 */



#include "bcm-phy-lib.h"

#include <linux/brcmphy.h>

#include <linux/export.h>

#include <linux/mdio.h>

#include <linux/phy.h>



#define MII_BCM_CHANNEL_WIDTH     0x2000

#define BCM_CL45VEN_EEE_ADV       0x3c



int bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val)

{

	int rc;



	rc = phy_write(phydev, MII_BCM54XX_EXP_SEL, reg);

	if (rc < 0)

		return rc;



	return phy_write(phydev, MII_BCM54XX_EXP_DATA, val);

}

EXPORT_SYMBOL_GPL(bcm_phy_write_exp);



int bcm_phy_read_exp(struct phy_device *phydev, u16 reg)

{

	int val;



	val = phy_write(phydev, MII_BCM54XX_EXP_SEL, reg);

	if (val < 0)

		return val;



	val = phy_read(phydev, MII_BCM54XX_EXP_DATA);



	/* Restore default value.  It's O.K. if this write fails. */

	phy_write(phydev, MII_BCM54XX_EXP_SEL, 0);



	return val;

}

EXPORT_SYMBOL_GPL(bcm_phy_read_exp);



int bcm_phy_write_misc(struct phy_device *phydev,

		       u16 reg, u16 chl, u16 val)

{

	int rc;

	int tmp;



	rc = phy_write(phydev, MII_BCM54XX_AUX_CTL,

		       MII_BCM54XX_AUXCTL_SHDWSEL_MISC);

	if (rc < 0)

		return rc;



	tmp = phy_read(phydev, MII_BCM54XX_AUX_CTL);

	tmp |= MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA;

	rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp);

	if (rc < 0)

		return rc;



	tmp = (chl * MII_BCM_CHANNEL_WIDTH) | reg;

	rc = bcm_phy_write_exp(phydev, tmp, val);



	return rc;

}

EXPORT_SYMBOL_GPL(bcm_phy_write_misc);



int bcm_phy_read_misc(struct phy_device *phydev,

		      u16 reg, u16 chl)

{

	int rc;

	int tmp;



	rc = phy_write(phydev, MII_BCM54XX_AUX_CTL,

		       MII_BCM54XX_AUXCTL_SHDWSEL_MISC);

	if (rc < 0)

		return rc;



	tmp = phy_read(phydev, MII_BCM54XX_AUX_CTL);

	tmp |= MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA;

	rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp);

	if (rc < 0)

		return rc;



	tmp = (chl * MII_BCM_CHANNEL_WIDTH) | reg;

	rc = bcm_phy_read_exp(phydev, tmp);



	return rc;

}

EXPORT_SYMBOL_GPL(bcm_phy_read_misc);



int bcm_phy_ack_intr(struct phy_device *phydev)

{

	int reg;



	/* Clear pending interrupts.  */

	reg = phy_read(phydev, MII_BCM54XX_ISR);

	if (reg < 0)

		return reg;



	return 0;

}

EXPORT_SYMBOL_GPL(bcm_phy_ack_intr);



int bcm_phy_config_intr(struct phy_device *phydev)

{

	int reg;



	reg = phy_read(phydev, MII_BCM54XX_ECR);

	if (reg < 0)

		return reg;



	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)

		reg &= ~MII_BCM54XX_ECR_IM;

	else

		reg |= MII_BCM54XX_ECR_IM;



	return phy_write(phydev, MII_BCM54XX_ECR, reg);

}

EXPORT_SYMBOL_GPL(bcm_phy_config_intr);



int bcm_phy_read_shadow(struct phy_device *phydev, u16 shadow)

{

	phy_write(phydev, MII_BCM54XX_SHD, MII_BCM54XX_SHD_VAL(shadow));

	return MII_BCM54XX_SHD_DATA(phy_read(phydev, MII_BCM54XX_SHD));

}

EXPORT_SYMBOL_GPL(bcm_phy_read_shadow);



int bcm_phy_write_shadow(struct phy_device *phydev, u16 shadow,

			 u16 val)

{

	return phy_write(phydev, MII_BCM54XX_SHD,

			 MII_BCM54XX_SHD_WRITE |

			 MII_BCM54XX_SHD_VAL(shadow) |

			 MII_BCM54XX_SHD_DATA(val));

}

EXPORT_SYMBOL_GPL(bcm_phy_write_shadow);



int bcm_phy_enable_apd(struct phy_device *phydev, bool dll_pwr_down)

{

	int val;



	if (dll_pwr_down) {

		val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3);

		if (val < 0)

			return val;



		val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;

		bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val);

	}



	val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD);

	if (val < 0)

		return val;



	/* Clear APD bits */

	val &= BCM_APD_CLR_MASK;



	if (phydev->autoneg == AUTONEG_ENABLE)

		val |= BCM54XX_SHD_APD_EN;

	else

		val |= BCM_NO_ANEG_APD_EN;



	/* Enable energy detect single link pulse for easy wakeup */

	val |= BCM_APD_SINGLELP_EN;



	/* Enable Auto Power-Down (APD) for the PHY */

	return bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val);

}

EXPORT_SYMBOL_GPL(bcm_phy_enable_apd);



int bcm_phy_enable_eee(struct phy_device *phydev)

{

	int val;



	/* Enable EEE at PHY level */

	val = phy_read_mmd_indirect(phydev, BRCM_CL45VEN_EEE_CONTROL,

				    MDIO_MMD_AN, phydev->addr);

	if (val < 0)

		return val;



	val |= LPI_FEATURE_EN | LPI_FEATURE_EN_DIG1000X;



	phy_write_mmd_indirect(phydev, BRCM_CL45VEN_EEE_CONTROL,

			       MDIO_MMD_AN,  phydev->addr, (u32)val);



	/* Advertise EEE */

	val = phy_read_mmd_indirect(phydev, BCM_CL45VEN_EEE_ADV,

				    MDIO_MMD_AN, phydev->addr);

	if (val < 0)

		return val;



	val |= (MDIO_AN_EEE_ADV_100TX | MDIO_AN_EEE_ADV_1000T);



	phy_write_mmd_indirect(phydev, BCM_CL45VEN_EEE_ADV,

			       MDIO_MMD_AN,  phydev->addr, (u32)val);



	return 0;

}

EXPORT_SYMBOL_GPL(bcm_phy_enable_eee);

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