Commit 4946166e authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'meson-clk-4.21-1' of https://github.com/BayLibre/clk-meson into clk-meson 

Pull amlogic meson clk driver updates from Neil Armstrong:

 - Add GX video clocks
 - Switch to HHI syscon for meson8b
 - Fix meson8b cpu clock
 - Add support for meson8b CPU scaling
 - Add Meson8b CPU post-dividers clocks

* tag 'meson-clk-4.21-1' of https://github.com/BayLibre/clk-meson:
  clk: meson: meson8b: add the CPU clock post divider clocks
  clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3
  clk: meson: clk-regmap: add read-only gate ops
  clk: meson: meson8b: allow changing the CPU clock tree
  clk: meson: meson8b: run from the XTAL when changing the CPU frequency
  clk: meson: meson8b: add support for more M/N values in sys_pll
  clk: meson: meson8b: mark the CPU clock as CLK_IS_CRITICAL
  clk: meson: meson8b: do not use cpu_div3 for cpu_scale_out_sel
  clk: meson: clk-pll: check if the clock is already enabled
  clk: meson: meson8b: fix the width of the cpu_scale_div clock
  clk: meson: meson8b: fix incorrect divider mapping in cpu_scale_table
  clk: meson: meson8b: use the HHI syscon if available
  dt-bindings: clock: meson8b: use the registers from the HHI syscon
  clk: meson-gxbb: Add video clocks
  dt-bindings: clk: meson-gxbb: Add Video clock bindings
  clk: meson-gxbb: Fix HDMI PLL for GXL SoCs
  clk: meson: Add vid_pll divider driver
  dt-bindings: clock: meson8b: export the CPU post dividers
parents 65102238 a7d19b05

Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt

+5 −8
Original line number Diff line number Diff line
@@ -9,15 +9,13 @@ Required Properties: 
	- "amlogic,meson8-clkc" for Meson8 (S802) SoCs

	- "amlogic,meson8b-clkc" for Meson8 (S805) SoCs

	- "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs

- reg: it must be composed by two tuples:

	0) physical base address of the xtal register and length of memory

	   mapped region.

	1) physical base address of the clock controller and length of memory

	   mapped region.



- #clock-cells: should be 1.

- #reset-cells: should be 1.



Parent node should have the following properties :

- compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon"

- reg: base address and size of the HHI system control register space.



Each clock is assigned an identifier and client nodes can use this identifier

to specify the clock which they consume. All available clocks are defined as

preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be
@@ -30,9 +28,8 @@ device tree sources). 


Example: Clock controller node:



	clkc: clock-controller@c1104000 {

	clkc: clock-controller {

		compatible = "amlogic,meson8b-clkc";

		reg = <0xc1108000 0x4>, <0xc1104000 0x460>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};

drivers/clk/meson/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
# Makefile for Meson specific clk

#



obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-phase.o

obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-phase.o vid-pll-div.o

obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO)	+= clk-triphase.o sclk-div.o

obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o

obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o

drivers/clk/meson/clk-pll.c

+19 −0
Original line number Diff line number Diff line
@@ -200,11 +200,28 @@ static void meson_clk_pll_init(struct clk_hw *hw) 
	}

}



static int meson_clk_pll_is_enabled(struct clk_hw *hw)

{

	struct clk_regmap *clk = to_clk_regmap(hw);

	struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);



	if (meson_parm_read(clk->map, &pll->rst) ||

	    !meson_parm_read(clk->map, &pll->en) ||

	    !meson_parm_read(clk->map, &pll->l))

		return 0;



	return 1;

}



static int meson_clk_pll_enable(struct clk_hw *hw)

{

	struct clk_regmap *clk = to_clk_regmap(hw);

	struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);



	/* do nothing if the PLL is already enabled */

	if (clk_hw_is_enabled(hw))

		return 0;



	/* Make sure the pll is in reset */

	meson_parm_write(clk->map, &pll->rst, 1);
@@ -288,10 +305,12 @@ const struct clk_ops meson_clk_pll_ops = { 
	.recalc_rate	= meson_clk_pll_recalc_rate,

	.round_rate	= meson_clk_pll_round_rate,

	.set_rate	= meson_clk_pll_set_rate,

	.is_enabled	= meson_clk_pll_is_enabled,

	.enable		= meson_clk_pll_enable,

	.disable	= meson_clk_pll_disable

};



const struct clk_ops meson_clk_pll_ro_ops = {

	.recalc_rate	= meson_clk_pll_recalc_rate,

	.is_enabled	= meson_clk_pll_is_enabled,

};

drivers/clk/meson/clk-regmap.c

+5 −0
Original line number Diff line number Diff line
@@ -50,6 +50,11 @@ const struct clk_ops clk_regmap_gate_ops = { 
};

EXPORT_SYMBOL_GPL(clk_regmap_gate_ops);



const struct clk_ops clk_regmap_gate_ro_ops = {

	.is_enabled = clk_regmap_gate_is_enabled,

};

EXPORT_SYMBOL_GPL(clk_regmap_gate_ro_ops);



static unsigned long clk_regmap_div_recalc_rate(struct clk_hw *hw,

						unsigned long prate)

{

drivers/clk/meson/clk-regmap.h

+1 −0
Original line number Diff line number Diff line
@@ -51,6 +51,7 @@ clk_get_regmap_gate_data(struct clk_regmap *clk) 
}



extern const struct clk_ops clk_regmap_gate_ops;

extern const struct clk_ops clk_regmap_gate_ro_ops;



/**

 * struct clk_regmap_div_data - regmap backed adjustable divider specific data

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