Commit 4936ce17 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mtd/fixes-for-5.5-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux 

Pull MTD fixes from Miquel Raynal:
 "MTD:
   - sm_ftl: Fix NULL pointer warning.

  Raw NAND:
   - Cadence: fix compile testing.
   - STM32: Avoid locking.

  Onenand:
   - Fix several sparse/build warnings.

  SPI-NOR:
   - Add a flag to fix interaction with Micron parts"

* tag 'mtd/fixes-for-5.5-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux:
  mtd: spi-nor: Fix the writing of the Status Register on micron flashes
  mtd: sm_ftl: fix NULL pointer warning
  mtd: onenand: omap2: Pass correct flags for prep_dma_memcpy
  mtd: onenand: samsung: Fix iomem access with regular memcpy
  mtd: onenand: omap2: Fix errors in style
  mtd: cadence: Fix cast to pointer from integer of different size warning
  mtd: rawnand: stm32_fmc2: avoid to lock the CPU bus
parents b1d198c0 82de6a6f

drivers/mtd/nand/onenand/omap2.c

+8 −6
Original line number Diff line number Diff line
@@ -148,13 +148,13 @@ static int omap2_onenand_wait(struct mtd_info *mtd, int state) 
	unsigned long timeout;

	u32 syscfg;



	if (state == FL_RESETING || state == FL_PREPARING_ERASE ||

	if (state == FL_RESETTING || state == FL_PREPARING_ERASE ||

	    state == FL_VERIFYING_ERASE) {

		int i = 21;

		unsigned int intr_flags = ONENAND_INT_MASTER;



		switch (state) {

		case FL_RESETING:

		case FL_RESETTING:

			intr_flags |= ONENAND_INT_RESET;

			break;

		case FL_PREPARING_ERASE:
@@ -328,7 +328,8 @@ static inline int omap2_onenand_dma_transfer(struct omap2_onenand *c, 
	struct dma_async_tx_descriptor *tx;

	dma_cookie_t cookie;



	tx = dmaengine_prep_dma_memcpy(c->dma_chan, dst, src, count, 0);

	tx = dmaengine_prep_dma_memcpy(c->dma_chan, dst, src, count,

				       DMA_CTRL_ACK | DMA_PREP_INTERRUPT);

	if (!tx) {

		dev_err(&c->pdev->dev, "Failed to prepare DMA memcpy\n");

		return -EIO;
@@ -528,7 +529,8 @@ static int omap2_onenand_probe(struct platform_device *pdev) 
		 c->gpmc_cs, c->phys_base, c->onenand.base,

		 c->dma_chan ? "DMA" : "PIO");



	if ((r = onenand_scan(&c->mtd, 1)) < 0)

	r = onenand_scan(&c->mtd, 1);

	if (r < 0)

		goto err_release_dma;



	freq = omap2_onenand_get_freq(c->onenand.version_id);

drivers/mtd/nand/onenand/onenand_base.c

+7 −7
Original line number Diff line number Diff line
@@ -2853,7 +2853,7 @@ static int onenand_otp_write_oob_nolock(struct mtd_info *mtd, loff_t to, 


		/* Exit OTP access mode */

		this->command(mtd, ONENAND_CMD_RESET, 0, 0);

		this->wait(mtd, FL_RESETING);

		this->wait(mtd, FL_RESETTING);



		status = this->read_word(this->base + ONENAND_REG_CTRL_STATUS);

		status &= 0x60;
@@ -2924,7 +2924,7 @@ static int do_otp_read(struct mtd_info *mtd, loff_t from, size_t len, 


	/* Exit OTP access mode */

	this->command(mtd, ONENAND_CMD_RESET, 0, 0);

	this->wait(mtd, FL_RESETING);

	this->wait(mtd, FL_RESETTING);



	return ret;

}
@@ -2968,7 +2968,7 @@ static int do_otp_write(struct mtd_info *mtd, loff_t to, size_t len, 


	/* Exit OTP access mode */

	this->command(mtd, ONENAND_CMD_RESET, 0, 0);

	this->wait(mtd, FL_RESETING);

	this->wait(mtd, FL_RESETTING);



	return ret;

}
@@ -3008,7 +3008,7 @@ static int do_otp_lock(struct mtd_info *mtd, loff_t from, size_t len, 


		/* Exit OTP access mode */

		this->command(mtd, ONENAND_CMD_RESET, 0, 0);

		this->wait(mtd, FL_RESETING);

		this->wait(mtd, FL_RESETTING);

	} else {

		ops.mode = MTD_OPS_PLACE_OOB;

		ops.ooblen = len;
@@ -3413,7 +3413,7 @@ static int flexonenand_get_boundary(struct mtd_info *mtd) 
		this->boundary[die] = bdry & FLEXONENAND_PI_MASK;



		this->command(mtd, ONENAND_CMD_RESET, 0, 0);

		this->wait(mtd, FL_RESETING);

		this->wait(mtd, FL_RESETTING);



		printk(KERN_INFO "Die %d boundary: %d%s\n", die,

		       this->boundary[die], locked ? "(Locked)" : "(Unlocked)");
@@ -3635,7 +3635,7 @@ static int flexonenand_set_boundary(struct mtd_info *mtd, int die, 
	ret = this->wait(mtd, FL_WRITING);

out:

	this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_REG_COMMAND);

	this->wait(mtd, FL_RESETING);

	this->wait(mtd, FL_RESETTING);

	if (!ret)

		/* Recalculate device size on boundary change*/

		flexonenand_get_size(mtd);
@@ -3671,7 +3671,7 @@ static int onenand_chip_probe(struct mtd_info *mtd) 
	/* Reset OneNAND to read default register values */

	this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_BOOTRAM);

	/* Wait reset */

	this->wait(mtd, FL_RESETING);

	this->wait(mtd, FL_RESETTING);



	/* Restore system configuration 1 */

	this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1);

drivers/mtd/nand/onenand/samsung_mtd.c

+4 −4
Original line number Diff line number Diff line
@@ -675,12 +675,12 @@ static int s5pc110_read_bufferram(struct mtd_info *mtd, int area, 
normal:

	if (count != mtd->writesize) {

		/* Copy the bufferram to memory to prevent unaligned access */

		memcpy(this->page_buf, p, mtd->writesize);

		p = this->page_buf + offset;

		memcpy_fromio(this->page_buf, p, mtd->writesize);

		memcpy(buffer, this->page_buf + offset, count);

	} else {

		memcpy_fromio(buffer, p, count);

	}



	memcpy(buffer, p, count);



	return 0;

}

drivers/mtd/nand/raw/cadence-nand-controller.c

+6 −7
Original line number Diff line number Diff line
@@ -914,8 +914,8 @@ static void cadence_nand_get_caps(struct cdns_nand_ctrl *cdns_ctrl) 
/* Prepare CDMA descriptor. */

static void

cadence_nand_cdma_desc_prepare(struct cdns_nand_ctrl *cdns_ctrl,

			       char nf_mem, u32 flash_ptr, char *mem_ptr,

			       char *ctrl_data_ptr, u16 ctype)

			       char nf_mem, u32 flash_ptr, dma_addr_t mem_ptr,

				   dma_addr_t ctrl_data_ptr, u16 ctype)

{

	struct cadence_nand_cdma_desc *cdma_desc = cdns_ctrl->cdma_desc;
@@ -931,13 +931,13 @@ cadence_nand_cdma_desc_prepare(struct cdns_nand_ctrl *cdns_ctrl, 
	cdma_desc->command_flags |= CDMA_CF_DMA_MASTER;

	cdma_desc->command_flags  |= CDMA_CF_INT;



	cdma_desc->memory_pointer = (uintptr_t)mem_ptr;

	cdma_desc->memory_pointer = mem_ptr;

	cdma_desc->status = 0;

	cdma_desc->sync_flag_pointer = 0;

	cdma_desc->sync_arguments = 0;



	cdma_desc->command_type = ctype;

	cdma_desc->ctrl_data_ptr = (uintptr_t)ctrl_data_ptr;

	cdma_desc->ctrl_data_ptr = ctrl_data_ptr;

}



static u8 cadence_nand_check_desc_error(struct cdns_nand_ctrl *cdns_ctrl,
@@ -1280,8 +1280,7 @@ cadence_nand_cdma_transfer(struct cdns_nand_ctrl *cdns_ctrl, u8 chip_nr, 
	}



	cadence_nand_cdma_desc_prepare(cdns_ctrl, chip_nr, page,

				       (void *)dma_buf, (void *)dma_ctrl_dat,

				       ctype);

				       dma_buf, dma_ctrl_dat, ctype);



	status = cadence_nand_cdma_send_and_wait(cdns_ctrl, thread_nr);
@@ -1360,7 +1359,7 @@ static int cadence_nand_erase(struct nand_chip *chip, u32 page) 


	cadence_nand_cdma_desc_prepare(cdns_ctrl,

				       cdns_chip->cs[chip->cur_cs],

				       page, NULL, NULL,

				       page, 0, 0,

				       CDMA_CT_ERASE);

	status = cadence_nand_cdma_send_and_wait(cdns_ctrl, thread_nr);

	if (status) {

drivers/mtd/nand/raw/stm32_fmc2_nand.c

+36 −2
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ 
/* Max ECC buffer length */

#define FMC2_MAX_ECC_BUF_LEN		(FMC2_BCHDSRS_LEN * FMC2_MAX_SG)



#define FMC2_TIMEOUT_US			1000

#define FMC2_TIMEOUT_MS			1000



/* Timings */
@@ -53,6 +54,8 @@ 
#define FMC2_PMEM			0x88

#define FMC2_PATT			0x8c

#define FMC2_HECCR			0x94

#define FMC2_ISR			0x184

#define FMC2_ICR			0x188

#define FMC2_CSQCR			0x200

#define FMC2_CSQCFGR1			0x204

#define FMC2_CSQCFGR2			0x208
@@ -118,6 +121,12 @@ 
#define FMC2_PATT_ATTHIZ(x)		(((x) & 0xff) << 24)

#define FMC2_PATT_DEFAULT		0x0a0a0a0a



/* Register: FMC2_ISR */

#define FMC2_ISR_IHLF			BIT(1)



/* Register: FMC2_ICR */

#define FMC2_ICR_CIHLF			BIT(1)



/* Register: FMC2_CSQCR */

#define FMC2_CSQCR_CSQSTART		BIT(0)
@@ -1322,6 +1331,31 @@ static void stm32_fmc2_write_data(struct nand_chip *chip, const void *buf, 
		stm32_fmc2_set_buswidth_16(fmc2, true);

}



static int stm32_fmc2_waitrdy(struct nand_chip *chip, unsigned long timeout_ms)

{

	struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);

	const struct nand_sdr_timings *timings;

	u32 isr, sr;



	/* Check if there is no pending requests to the NAND flash */

	if (readl_relaxed_poll_timeout_atomic(fmc2->io_base + FMC2_SR, sr,

					      sr & FMC2_SR_NWRF, 1,

					      FMC2_TIMEOUT_US))

		dev_warn(fmc2->dev, "Waitrdy timeout\n");



	/* Wait tWB before R/B# signal is low */

	timings = nand_get_sdr_timings(&chip->data_interface);

	ndelay(PSEC_TO_NSEC(timings->tWB_max));



	/* R/B# signal is low, clear high level flag */

	writel_relaxed(FMC2_ICR_CIHLF, fmc2->io_base + FMC2_ICR);



	/* Wait R/B# signal is high */

	return readl_relaxed_poll_timeout_atomic(fmc2->io_base + FMC2_ISR,

						 isr, isr & FMC2_ISR_IHLF,

						 5, 1000 * timeout_ms);

}



static int stm32_fmc2_exec_op(struct nand_chip *chip,

			      const struct nand_operation *op,

			      bool check_only)
@@ -1366,7 +1400,7 @@ static int stm32_fmc2_exec_op(struct nand_chip *chip, 
			break;



		case NAND_OP_WAITRDY_INSTR:

			ret = nand_soft_waitrdy(chip,

			ret = stm32_fmc2_waitrdy(chip,

						 instr->ctx.waitrdy.timeout_ms);

			break;

		}

CRA Git | Maintained and supported by SUSTech CRA and CCSE