Commit 48ff08dd authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'renesas-drivers-for-v4.21' of... 

Merge tag 'renesas-drivers-for-v4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers

Renesas ARM Based SoC Drivers Updates for v4.21

SYSC Driver:
* Common
  - Fix power domain control after system resume
  - Merge PM Domain registration and linking
  - Remove rcar_sysc_power_{down,up}() helpers
* R-Car E3 (r8a77990) SoC
  - Fix initialization order of 3DG-{A,B}
* R-Car V3H (r8a77980) SoC
  - Correct A3VIP[012] power domain hierarchy
  - Correct names of A2DP[01] power domains
* R-Car V3M (r8a77970) SoC
  - Correct names of A2DP/A2CN power domains
  - emove non-existent CR7 power domain
* R-Car M3-N (r8a77965) SoC
  - Remove non-existent A3IR power domain

* tag 'renesas-drivers-for-v4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas

:
  soc: renesas: rcar-sysc: Fix power domain control after system resume
  soc: renesas: rcar-sysc: Merge PM Domain registration and linking
  soc: renesas: rcar-sysc: Remove rcar_sysc_power_{down,up}() helpers
  soc: renesas: r8a77990-sysc: Fix initialization order of 3DG-{A,B}
  soc: renesas: r8a77980-sysc: Correct A3VIP[012] power domain hierarchy
  soc: renesas: r8a77980-sysc: Correct names of A2DP[01] power domains
  soc: renesas: r8a77970-sysc: Correct names of A2DP/A2CN power domains
  soc: renesas: r8a77970-sysc: Remove non-existent CR7 power domain
  soc: renesas: r8a77965-sysc: Remove non-existent A3IR power domain

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 330a7809 7fc4650c

drivers/soc/renesas/r8a77965-sysc.c

+0 −1
Original line number Diff line number Diff line
@@ -28,7 +28,6 @@ static const struct rcar_sysc_area r8a77965_areas[] __initconst = { 
	{ "a2vc1",	0x3c0, 1, R8A77965_PD_A2VC1,	R8A77965_PD_A3VC },

	{ "3dg-a",	0x100, 0, R8A77965_PD_3DG_A,	R8A77965_PD_ALWAYS_ON },

	{ "3dg-b",	0x100, 1, R8A77965_PD_3DG_B,	R8A77965_PD_3DG_A },

	{ "a3ir",	0x180, 0, R8A77965_PD_A3IR,	R8A77965_PD_ALWAYS_ON },

};



const struct rcar_sysc_info r8a77965_sysc_info __initconst = {

drivers/soc/renesas/r8a77970-sysc.c

+2 −3
Original line number Diff line number Diff line
@@ -20,12 +20,11 @@ static const struct rcar_sysc_area r8a77970_areas[] __initconst = { 
	  PD_CPU_NOCR },

	{ "ca53-cpu1",	0x200, 1, R8A77970_PD_CA53_CPU1, R8A77970_PD_CA53_SCU,

	  PD_CPU_NOCR },

	{ "cr7",	0x240, 0, R8A77970_PD_CR7,	R8A77970_PD_ALWAYS_ON },

	{ "a3ir",	0x180, 0, R8A77970_PD_A3IR,	R8A77970_PD_ALWAYS_ON },

	{ "a2ir0",	0x400, 0, R8A77970_PD_A2IR0,	R8A77970_PD_A3IR },

	{ "a2ir1",	0x400, 1, R8A77970_PD_A2IR1,	R8A77970_PD_A3IR },

	{ "a2ir2",	0x400, 2, R8A77970_PD_A2IR2,	R8A77970_PD_A3IR },

	{ "a2ir3",	0x400, 3, R8A77970_PD_A2IR3,	R8A77970_PD_A3IR },

	{ "a2dp",	0x400, 2, R8A77970_PD_A2DP,	R8A77970_PD_A3IR },

	{ "a2cn",	0x400, 3, R8A77970_PD_A2CN,	R8A77970_PD_A3IR },

	{ "a2sc0",	0x400, 4, R8A77970_PD_A2SC0,	R8A77970_PD_A3IR },

	{ "a2sc1",	0x400, 5, R8A77970_PD_A2SC1,	R8A77970_PD_A3IR },

};

drivers/soc/renesas/r8a77980-sysc.c

+5 −5
Original line number Diff line number Diff line
@@ -38,12 +38,12 @@ static const struct rcar_sysc_area r8a77980_areas[] __initconst = { 
	{ "a2sc2",	0x400, 8, R8A77980_PD_A2SC2,	R8A77980_PD_A3IR },

	{ "a2sc3",	0x400, 9, R8A77980_PD_A2SC3,	R8A77980_PD_A3IR },

	{ "a2sc4",	0x400, 10, R8A77980_PD_A2SC4,	R8A77980_PD_A3IR },

	{ "a2pd0",	0x400, 11, R8A77980_PD_A2PD0,	R8A77980_PD_A3IR },

	{ "a2pd1",	0x400, 12, R8A77980_PD_A2PD1,	R8A77980_PD_A3IR },

	{ "a2dp0",	0x400, 11, R8A77980_PD_A2DP0,	R8A77980_PD_A3IR },

	{ "a2dp1",	0x400, 12, R8A77980_PD_A2DP1,	R8A77980_PD_A3IR },

	{ "a2cn",	0x400, 13, R8A77980_PD_A2CN,	R8A77980_PD_A3IR },

	{ "a3vip",	0x2c0, 0, R8A77980_PD_A3VIP,	R8A77980_PD_ALWAYS_ON },

	{ "a3vip1",	0x300, 0, R8A77980_PD_A3VIP1,	R8A77980_PD_A3VIP },

	{ "a3vip2",	0x280, 0, R8A77980_PD_A3VIP2,	R8A77980_PD_A3VIP },

	{ "a3vip0",	0x2c0, 0, R8A77980_PD_A3VIP0,	R8A77980_PD_ALWAYS_ON },

	{ "a3vip1",	0x300, 0, R8A77980_PD_A3VIP1,	R8A77980_PD_ALWAYS_ON },

	{ "a3vip2",	0x280, 0, R8A77980_PD_A3VIP2,	R8A77980_PD_ALWAYS_ON },

};



const struct rcar_sysc_info r8a77980_sysc_info __initconst = {

drivers/soc/renesas/r8a77990-sysc.c

+4 −19
Original line number Diff line number Diff line
@@ -28,19 +28,6 @@ static struct rcar_sysc_area r8a77990_areas[] __initdata = { 
	{ "3dg-b",	0x100, 1, R8A77990_PD_3DG_B,	R8A77990_PD_3DG_A },

};



static void __init rcar_sysc_fix_parent(struct rcar_sysc_area *areas,

					unsigned int num_areas, u8 id,

					int new_parent)

{

	unsigned int i;



	for (i = 0; i < num_areas; i++)

		if (areas[i].isr_bit == id) {

			areas[i].parent = new_parent;

			return;

		}

}



/* Fixups for R-Car E3 ES1.0 revision */

static const struct soc_device_attribute r8a77990[] __initconst = {

	{ .soc_id = "r8a77990", .revision = "ES1.0" },
@@ -50,12 +37,10 @@ static const struct soc_device_attribute r8a77990[] __initconst = { 
static int __init r8a77990_sysc_init(void)

{

	if (soc_device_match(r8a77990)) {

		rcar_sysc_fix_parent(r8a77990_areas,

				     ARRAY_SIZE(r8a77990_areas),

				     R8A77990_PD_3DG_A, R8A77990_PD_3DG_B);

		rcar_sysc_fix_parent(r8a77990_areas,

				     ARRAY_SIZE(r8a77990_areas),

				     R8A77990_PD_3DG_B, R8A77990_PD_ALWAYS_ON);

		/* Fix incorrect 3DG hierarchy */

		swap(r8a77990_areas[7], r8a77990_areas[8]);

		r8a77990_areas[7].parent = R8A77990_PD_ALWAYS_ON;

		r8a77990_areas[8].parent = R8A77990_PD_3DG_B;

	}



	return 0;

drivers/soc/renesas/rcar-sysc.c

+18 −47
Original line number Diff line number Diff line
@@ -105,6 +105,15 @@ static int rcar_sysc_power(const struct rcar_sysc_ch *sysc_ch, bool on) 


	spin_lock_irqsave(&rcar_sysc_lock, flags);



	/*

	 * The interrupt source needs to be enabled, but masked, to prevent the

	 * CPU from receiving it.

	 */

	iowrite32(ioread32(rcar_sysc_base + SYSCIMR) | isr_mask,

		  rcar_sysc_base + SYSCIMR);

	iowrite32(ioread32(rcar_sysc_base + SYSCIER) | isr_mask,

		  rcar_sysc_base + SYSCIER);



	iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);



	/* Submit power shutoff or resume request until it was accepted */
@@ -146,16 +155,6 @@ static int rcar_sysc_power(const struct rcar_sysc_ch *sysc_ch, bool on) 
	return ret;

}



static int rcar_sysc_power_down(const struct rcar_sysc_ch *sysc_ch)

{

	return rcar_sysc_power(sysc_ch, false);

}



static int rcar_sysc_power_up(const struct rcar_sysc_ch *sysc_ch)

{

	return rcar_sysc_power(sysc_ch, true);

}



static bool rcar_sysc_power_is_off(const struct rcar_sysc_ch *sysc_ch)

{

	unsigned int st;
@@ -184,7 +183,7 @@ static int rcar_sysc_pd_power_off(struct generic_pm_domain *genpd) 
	struct rcar_sysc_pd *pd = to_rcar_pd(genpd);



	pr_debug("%s: %s\n", __func__, genpd->name);

	return rcar_sysc_power_down(&pd->ch);

	return rcar_sysc_power(&pd->ch, false);

}



static int rcar_sysc_pd_power_on(struct generic_pm_domain *genpd)
@@ -192,7 +191,7 @@ static int rcar_sysc_pd_power_on(struct generic_pm_domain *genpd) 
	struct rcar_sysc_pd *pd = to_rcar_pd(genpd);



	pr_debug("%s: %s\n", __func__, genpd->name);

	return rcar_sysc_power_up(&pd->ch);

	return rcar_sysc_power(&pd->ch, true);

}



static bool has_cpg_mstp;
@@ -252,7 +251,7 @@ static int __init rcar_sysc_pd_setup(struct rcar_sysc_pd *pd) 
		goto finalize;

	}



	rcar_sysc_power_up(&pd->ch);

	rcar_sysc_power(&pd->ch, true);



finalize:

	error = pm_genpd_init(genpd, gov, false);
@@ -334,7 +333,6 @@ static int __init rcar_sysc_pd_init(void) 
	const struct of_device_id *match;

	struct rcar_pm_domains *domains;

	struct device_node *np;

	u32 syscier, syscimr;

	void __iomem *base;

	unsigned int i;

	int error;
@@ -373,27 +371,6 @@ static int __init rcar_sysc_pd_init(void) 
	domains->onecell_data.num_domains = ARRAY_SIZE(domains->domains);

	rcar_sysc_onecell_data = &domains->onecell_data;



	for (i = 0, syscier = 0; i < info->num_areas; i++)

		syscier |= BIT(info->areas[i].isr_bit);



	/*

	 * Mask all interrupt sources to prevent the CPU from receiving them.

	 * Make sure not to clear reserved bits that were set before.

	 */

	syscimr = ioread32(base + SYSCIMR);

	syscimr |= syscier;

	pr_debug("%pOF: syscimr = 0x%08x\n", np, syscimr);

	iowrite32(syscimr, base + SYSCIMR);



	/*

	 * SYSC needs all interrupt sources enabled to control power.

	 */

	pr_debug("%pOF: syscier = 0x%08x\n", np, syscier);

	iowrite32(syscier, base + SYSCIER);



	/*

	 * First, create all PM domains

	 */

	for (i = 0; i < info->num_areas; i++) {

		const struct rcar_sysc_area *area = &info->areas[i];

		struct rcar_sysc_pd *pd;
@@ -421,22 +398,17 @@ static int __init rcar_sysc_pd_init(void) 
			goto out_put;



		domains->domains[area->isr_bit] = &pd->genpd;

	}



	/*

	 * Second, link all PM domains to their parents

	 */

	for (i = 0; i < info->num_areas; i++) {

		const struct rcar_sysc_area *area = &info->areas[i];



		if (!area->name || area->parent < 0)

		if (area->parent < 0)

			continue;



		error = pm_genpd_add_subdomain(domains->domains[area->parent],

					       domains->domains[area->isr_bit]);

		if (error)

					       &pd->genpd);

		if (error) {

			pr_warn("Failed to add PM subdomain %s to parent %u\n",

				area->name, area->parent);

			goto out_put;

		}

	}



	error = of_genpd_add_provider_onecell(np, &domains->onecell_data);
@@ -478,8 +450,7 @@ static int rcar_sysc_power_cpu(unsigned int idx, bool on) 
		if (!(pd->flags & PD_CPU) || pd->ch.chan_bit != idx)

			continue;



		return on ? rcar_sysc_power_up(&pd->ch)

			  : rcar_sysc_power_down(&pd->ch);

		return rcar_sysc_power(&pd->ch, on);

	}



	return -ENOENT;

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