Commit 48f68de0 authored Dec 02, 2020 by Jernej Skrabec Committed by Stephen Boyd Dec 19, 2020

clk: sunxi-ng: Make sure divider tables have sentinel



Two clock divider tables are missing sentinel at the end. Effect of that
is that clock framework reads past the last entry. Fix that with adding
sentinel at the end.

Issue was discovered with KASan.

Fixes: 0577e485 ("clk: sunxi-ng: Add H3 clocks")
Fixes: c6a06374 ("clk: sunxi-ng: Add A64 clocks")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Link: https://lore.kernel.org/r/20201202203817.438713-1-jernej.skrabec@siol.net


Acked-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

parent d2d94fc5

drivers/clk/sunxi-ng/ccu-sun50i-a64.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -389,6 +389,7 @@ static struct clk_div_table ths_div_table[] = {
		{ .val = 1, .div = 2 },
		{ .val = 2, .div = 4 },
		{ .val = 3, .div = 6 },
		{ /* Sentinel */ },
		};
		static const char * const ths_parents[] = { "osc24M" };
		static struct ccu_div ths_clk = {

drivers/clk/sunxi-ng/ccu-sun8i-h3.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -322,6 +322,7 @@ static struct clk_div_table ths_div_table[] = {
		{ .val = 1, .div = 2 },
		{ .val = 2, .div = 4 },
		{ .val = 3, .div = 6 },
		{ /* Sentinel */ },
		};
		static SUNXI_CCU_DIV_TABLE_WITH_GATE(ths_clk, "ths", "osc24M",
		0x074, 0, 2, ths_div_table, BIT(31), 0);

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