Commit 48ed33c1 authored Aug 19, 2016 by Paul Burton Committed by Ralf Baechle Jan 03, 2017

MIPS: sc-mips: L2 cache is inclusive of L1 dcache for CM3



In systems with CM3 & higher, the L2 cache is inclusive of the L1
dcache. Indicate this such that cpu_has_inclusive_pcaches evaluates true
and we avoid some unnecessary cache ops during DMA cache maintenance.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14018/


Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent d66f99bc

arch/mips/mm/sc-mips.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -181,6 +181,7 @@ static int __init mips_sc_probe_cm3(void)

		if (c->scache.linesz) {
		c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
		c->options \|= MIPS_CPU_INCLUSIVE_CACHES;
		return 1;
		}

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