drm/amd/display: enable hostvm based on roimmu active for dcn2.1 (48d92e8e) · Commits · 戴 / test

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c

+25 −15

Original line number	Diff line number	Diff line
		@@ -22,6 +22,7 @@
		* Authors: AMD
		*
		*/
		#include <linux/delay.h>
		#include "dm_services.h"
		#include "dcn20/dcn20_hubbub.h"
		#include "dcn21_hubbub.h"
		@@ -71,14 +72,23 @@ static uint32_t convert_and_clamp(
		void dcn21_dchvm_init(struct hubbub *hubbub)
		{
		struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
		uint32_t riommu_active;
		int i;

		//Init DCHVM block
		REG_UPDATE(DCHVM_CTRL0, HOSTVM_INIT_REQ, 1);

		//Poll until RIOMMU_ACTIVE = 1
		//TODO: Figure out interval us and retry count
		REG_WAIT(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, 1, 5, 100);
		for (i = 0; i < 100; i++) {
		REG_GET(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, &riommu_active);

		if (riommu_active)
		break;
		else
		udelay(5);
		}

		if (riommu_active) {
		//Reflect the power status of DCHUBBUB
		REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, 1);

		@@ -93,9 +103,9 @@ void dcn21_dchvm_init(struct hubbub *hubbub)
		HVM_DCFCLK_G_GATE_DIS, 0);

		//Poll until HOSTVM_PREFETCH_DONE = 1
		//TODO: Figure out interval us and retry count
		REG_WAIT(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, 1, 5, 100);
		}
		}

		int hubbub21_init_dchub(struct hubbub *hubbub,
		struct dcn_hubbub_phys_addr_config *pa_config)