Commit 48d10bda authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'usb-4.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb 

Pull USB updates from Greg KH:
 "Here is the big USB patchset for 4.6-rc1.

  The normal mess is here, gadget and xhci fixes and updates, and lots
  of other driver updates and cleanups as well.  Full details are in the
  shortlog.

  All have been in linux-next for a while with no reported issues"

* tag 'usb-4.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (266 commits)
  USB: core: let USB device know device node
  usb: devio: Add ioctl to disallow detaching kernel USB drivers.
  usb: gadget: f_acm: Fix configfs attr name
  usb: udc: lpc32xx: remove USB PLL and USB OTG clock management
  usb: udc: lpc32xx: remove direct access to clock controller registers
  usb: udc: lpc32xx: switch to clock prepare/unprepare model
  usb: renesas_usbhs: gadget: fix giveback status code in usbhsg_pipe_disable()
  usb: gadget: renesas_usb3: Use ARCH_RENESAS
  usb: dwc2: Fix issues in dwc2_complete_non_isoc_xfer_ddma()
  usb: dwc2: Add support for Lantiq ARX and XRX SoCs
  usb: phy: generic: Handle late registration of gadget
  usb: gadget: bdc_udc: fix race condition in bdc_udc_exit()
  usb: musb: core: added missing const qualifier to musb_hdrc_platform_data::config
  usb: dwc2: Move host-specific core functions into hcd.c
  usb: dwc2: Move register save and restore functions
  usb: dwc2: Use kmem_cache_free()
  usb: dwc2: host: If using uframe scheduler, end splits better
  usb: dwc2: host: Totally redo the microframe scheduler
  usb: dwc2: host: Properly set even/odd frame
  usb: dwc2: host: Add dwc2_hcd_get_future_frame_number() call
  ...
parents 96b9b1c9 ce53bfc4

Documentation/DocBook/usb.tmpl

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@@ -732,6 +732,18 @@ usbdev_ioctl (int fd, int ifno, unsigned request, void *param) 
		    or SET_INTERFACE.

		    </para></warning></listitem></varlistentry>



		<varlistentry><term>USBDEVFS_DROP_PRIVILEGES</term>

		    <listitem><para>This is used to relinquish the ability

		    to do certain operations which are considered to be

		    privileged on a usbfs file descriptor.

		    This includes claiming arbitrary interfaces, resetting

		    a device on which there are currently claimed interfaces

		    from other users, and issuing USBDEVFS_IOCTL calls.

		    The ioctl parameter is a 32 bit mask of interfaces

		    the user is allowed to claim on this file descriptor.

		    You may issue this ioctl more than one time to narrow

		    said mask.

		    </para></listitem></varlistentry>

		</variablelist>



		</sect2>

Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt

+4 −11
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@@ -7,33 +7,26 @@ Required properties: 
- compatible: "renesas,usb2-phy-r8a7795" if the device is a part of an R8A7795

	      SoC.

- reg: offset and length of the partial USB 2.0 Host register block.

- reg-names: must be "usb2_host".

- clocks: clock phandle and specifier pair(s).

- #phy-cells: see phy-bindings.txt in the same directory, must be <0>.



Optional properties:

To use a USB channel where USB 2.0 Host and HSUSB (USB 2.0 Peripheral) are

combined, the device tree node should set HSUSB properties to reg and reg-names

properties. This is because HSUSB has registers to select USB 2.0 host or

peripheral at that channel:

- reg: offset and length of the partial HSUSB register block.

- reg-names: must be "hsusb".

combined, the device tree node should set interrupt properties to use the

channel as USB OTG:

- interrupts: interrupt specifier for the PHY.



Example (R-Car H3):



	usb-phy@ee080200 {

		compatible = "renesas,usb2-phy-r8a7795";

		reg = <0 0xee080200 0 0x700>, <0 0xe6590100 0 0x100>;

		reg-names = "usb2_host", "hsusb";

		reg = <0 0xee080200 0 0x700>;

		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp7_clks R8A7795_CLK_EHCI0>,

			 <&mstp7_clks R8A7795_CLK_HSUSB>;

		clocks = <&mstp7_clks R8A7795_CLK_EHCI0>;

	};



	usb-phy@ee0a0200 {

		compatible = "renesas,usb2-phy-r8a7795";

		reg = <0 0xee0a0200 0 0x700>;

		reg-names = "usb2_host";

		clocks = <&mstp7_clks R8A7795_CLK_EHCI0>;

	};

Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt

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+22 −0
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Rockchip specific extensions to the Analogix Display Port PHY

------------------------------------



Required properties:

- compatible : should be one of the following supported values:

	 - "rockchip.rk3288-dp-phy"

- clocks: from common clock binding: handle to dp clock.

	of memory mapped region.

- clock-names: from common clock binding:

	Required elements: "24m"

- rockchip,grf: phandle to the syscon managing the "general register files"

- #phy-cells : from the generic PHY bindings, must be 0;



Example:



edp_phy: edp-phy {

	compatible = "rockchip,rk3288-dp-phy";

	rockchip,grf = <&grf>;

	clocks = <&cru SCLK_EDP_24M>;

	clock-names = "24m";

	#phy-cells = <0>;

};

Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt

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+19 −0
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Rockchip EMMC PHY

-----------------------



Required properties:

 - compatible: rockchip,rk3399-emmc-phy

 - rockchip,grf : phandle to the syscon managing the "general

   register files"

 - #phy-cells: must be 0

 - reg: PHY configure reg address offset in "general

   register files"



Example:



emmcphy: phy {

	compatible = "rockchip,rk3399-emmc-phy";

	rockchip,grf = <&grf>;

	reg = <0xf780>;

	#phy-cells = <0>;

};

Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt

+23 −0
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@@ -2,7 +2,14 @@ 


Required properties:

- compatible: should be one of:

	"fsl,imx23-usb"

	"fsl,imx27-usb"

	"fsl,imx28-usb"

	"fsl,imx6q-usb"

	"fsl,imx6sl-usb"

	"fsl,imx6sx-usb"

	"fsl,imx6ul-usb"

	"fsl,imx7d-usb"

	"lsi,zevio-usb"

	"qcom,ci-hdrc"

	"chipidea,usb2"
@@ -53,6 +60,22 @@ Optional properties: 
  be specified.

- phy-clkgate-delay-us: the delay time (us) between putting the PHY into

  low power mode and gating the PHY clock.

- non-zero-ttctrl-ttha: after setting this property, the value of register

  ttctrl.ttha will be 0x7f; if not, the value will be 0x0, this is the default

  value. It needs to be very carefully for setting this property, it is

  recommended that consult with your IC engineer before setting this value.

  On the most of chipidea platforms, the "usage_tt" flag at RTL is 0, so this

  property only affects siTD.

  If this property is not set, the max packet size is 1023 bytes, and if

  the total of packet size for pervious transactions are more than 256 bytes,

  it can't accept any transactions within this frame. The use case is single

  transaction, but higher frame rate.

  If this property is set, the max packet size is 188 bytes, it can handle

  more transactions than above case, it can accept transactions until it

  considers the left room size within frame is less than 188 bytes, software

  needs to make sure it does not send more than 90%

  maximum_periodic_data_per_frame. The use case is multiple transactions, but

  less frame rate.



i.mx specific properties

- fsl,usbmisc: phandler of non-core register device, with one

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