Commit 48bc5562 authored by Jacob Pan's avatar Jacob Pan Committed by Ingo Molnar
Browse files

x86,mrst: Power control commands update 



On the Intel MID devices SCU commands are issued to manage power
off and the like. We need to issue different ones for
non-Lincroft based devices.

Signed-off-by: default avatarAlek Du <alek.du@intel.com>
Signed-off-by: default avatarJacob Pan <jacob.jun.pan@linux.intel.com>
Signed-off-by: default avatarAlan Cox <alan@linux.intel.com>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 6be30bb7

arch/x86/include/asm/intel_scu_ipc.h

+9 −5
Original line number Diff line number Diff line
@@ -3,8 +3,12 @@ 


#include <linux/notifier.h>



#define IPCMSG_VRTC	0xFA	 /* Set vRTC device */

#define IPCMSG_WARM_RESET	0xF0

#define IPCMSG_COLD_RESET	0xF1

#define IPCMSG_SOFT_RESET	0xF2

#define IPCMSG_COLD_BOOT	0xF3



#define IPCMSG_VRTC		0xFA	 /* Set vRTC device */

	/* Command id associated with message IPCMSG_VRTC */

	#define IPC_CMD_VRTC_SETTIME      1 /* Set time */

	#define IPC_CMD_VRTC_SETALARM     2 /* Set alarm */

arch/x86/platform/mrst/mrst.c

+14 −11
Original line number Diff line number Diff line
@@ -76,6 +76,20 @@ struct sfi_rtc_table_entry sfi_mrtc_array[SFI_MRTC_MAX]; 
EXPORT_SYMBOL_GPL(sfi_mrtc_array);

int sfi_mrtc_num;



static void mrst_power_off(void)

{

	if (__mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT)

		intel_scu_ipc_simple_command(IPCMSG_COLD_RESET, 1);

}



static void mrst_reboot(void)

{

	if (__mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT)

		intel_scu_ipc_simple_command(IPCMSG_COLD_RESET, 0);

	else

		intel_scu_ipc_simple_command(IPCMSG_COLD_BOOT, 0);

}



/* parse all the mtimer info to a static mtimer array */

static int __init sfi_parse_mtmr(struct sfi_table_header *table)

{
@@ -265,17 +279,6 @@ static int mrst_i8042_detect(void) 
	return 0;

}



/* Reboot and power off are handled by the SCU on a MID device */

static void mrst_power_off(void)

{

	intel_scu_ipc_simple_command(0xf1, 1);

}



static void mrst_reboot(void)

{

	intel_scu_ipc_simple_command(0xf1, 0);

}



/*

 * Moorestown does not have external NMI source nor port 0x61 to report

 * NMI status. The possible NMI sources are from pmu as a result of NMI

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