Commit 488f94d7 authored by Jintack Lim's avatar Jintack Lim Committed by Marc Zyngier
Browse files

KVM: arm64: Access CNTHCTL_EL2 bit fields correctly on VHE systems 



Current KVM world switch code is unintentionally setting wrong bits to
CNTHCTL_EL2 when E2H == 1, which may allow guest OS to access physical
timer.  Bit positions of CNTHCTL_EL2 are changing depending on
HCR_EL2.E2H bit.  EL1PCEN and EL1PCTEN are 1st and 0th bits when E2H is
not set, but they are 11th and 10th bits respectively when E2H is set.

In fact, on VHE we only need to set those bits once, not for every world
switch. This is because the host kernel runs in EL2 with HCR_EL2.TGE ==
1, which makes those bits have no effect for the host kernel execution.
So we just set those bits once for guests, and that's it.

Signed-off-by: default avatarJintack Lim <jintack@cs.columbia.edu>
Reviewed-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
parent 63e41226

arch/arm/include/asm/virt.h

+5 −0
Original line number Diff line number Diff line
@@ -80,6 +80,11 @@ static inline bool is_kernel_in_hyp_mode(void) 
	return false;

}



static inline bool has_vhe(void)

{

	return false;

}



/* The section containing the hypervisor idmap text */

extern char __hyp_idmap_text_start[];

extern char __hyp_idmap_text_end[];

arch/arm/kvm/arm.c

+3 −0
Original line number Diff line number Diff line
@@ -1099,6 +1099,9 @@ static void cpu_init_hyp_mode(void *dummy) 
	__cpu_init_hyp_mode(pgd_ptr, hyp_stack_ptr, vector_ptr);

	__cpu_init_stage2();



	if (is_kernel_in_hyp_mode())

		kvm_timer_init_vhe();



	kvm_arm_init_debug();

}

arch/arm64/include/asm/virt.h

+9 −0
Original line number Diff line number Diff line
@@ -47,6 +47,7 @@ 
#include <asm/ptrace.h>

#include <asm/sections.h>

#include <asm/sysreg.h>

#include <asm/cpufeature.h>



/*

 * __boot_cpu_mode records what mode CPUs were booted in.
@@ -80,6 +81,14 @@ static inline bool is_kernel_in_hyp_mode(void) 
	return read_sysreg(CurrentEL) == CurrentEL_EL2;

}



static inline bool has_vhe(void)

{

	if (cpus_have_const_cap(ARM64_HAS_VIRT_HOST_EXTN))

		return true;



	return false;

}



#ifdef CONFIG_ARM64_VHE

extern void verify_cpu_run_el(void);

#else

include/kvm/arm_arch_timer.h

+1 −0
Original line number Diff line number Diff line
@@ -76,4 +76,5 @@ void kvm_timer_unschedule(struct kvm_vcpu *vcpu); 


void kvm_timer_vcpu_put(struct kvm_vcpu *vcpu);



void kvm_timer_init_vhe(void);

#endif

virt/kvm/arm/arch_timer.c

+23 −0
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ 


#include <clocksource/arm_arch_timer.h>

#include <asm/arch_timer.h>

#include <asm/kvm_hyp.h>



#include <kvm/arm_vgic.h>

#include <kvm/arm_arch_timer.h>
@@ -509,3 +510,25 @@ void kvm_timer_init(struct kvm *kvm) 
{

	kvm->arch.timer.cntvoff = kvm_phys_timer_read();

}



/*

 * On VHE system, we only need to configure trap on physical timer and counter

 * accesses in EL0 and EL1 once, not for every world switch.

 * The host kernel runs at EL2 with HCR_EL2.TGE == 1,

 * and this makes those bits have no effect for the host kernel execution.

 */

void kvm_timer_init_vhe(void)

{

	/* When HCR_EL2.E2H ==1, EL1PCEN and EL1PCTEN are shifted by 10 */

	u32 cnthctl_shift = 10;

	u64 val;



	/*

	 * Disallow physical timer access for the guest.

	 * Physical counter access is allowed.

	 */

	val = read_sysreg(cnthctl_el2);

	val &= ~(CNTHCTL_EL1PCEN << cnthctl_shift);

	val |= (CNTHCTL_EL1PCTEN << cnthctl_shift);

	write_sysreg(val, cnthctl_el2);

}

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