Commit 48367432 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel 

Just a few small things:
- 2x workaround bits from Chris to fix up the new scanline waits enabled
  in 3.8 on snb. People who've been struck by this on dual-screen also
  need to upgrade the ddx.
- Dump the kernel version into i915_error_state, we've had a few mixups
  there recently.
- Disable gfx DMAR on gen4 devices, acked by David Woodhouse.

* 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel:
  drm/i915: dump UTS_RELEASE into the error_state
  iommu/intel: disable DMAR for g4x integrated gfx
  drm/i915: GFX_MODE Flush TLB Invalidate Mode must be '1' for scanline waits
  drm/i915: Disable AsyncFlip performance optimisations
parents f0f21aa5 4518f611

drivers/gpu/drm/i915/i915_debugfs.c

+2 −0
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ 
#include <linux/debugfs.h>

#include <linux/slab.h>

#include <linux/export.h>

#include <generated/utsrelease.h>

#include <drm/drmP.h>

#include "intel_drv.h"

#include "intel_ringbuffer.h"
@@ -690,6 +691,7 @@ static int i915_error_state(struct seq_file *m, void *unused) 


	seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,

		   error->time.tv_usec);

	seq_printf(m, "Kernel: " UTS_RELEASE);

	seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);

	seq_printf(m, "EIR: 0x%08x\n", error->eir);

	seq_printf(m, "IER: 0x%08x\n", error->ier);

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -533,6 +533,7 @@ 
#define MI_MODE		0x0209c

# define VS_TIMER_DISPATCH				(1 << 6)

# define MI_FLUSH_ENABLE				(1 << 12)

# define ASYNC_FLIP_PERF_DISABLE			(1 << 14)



#define GEN6_GT_MODE	0x20d0

#define   GEN6_GT_MODE_HI				(1 << 9)

drivers/gpu/drm/i915/intel_ringbuffer.c

+18 −6
Original line number Diff line number Diff line
@@ -505,13 +505,25 @@ static int init_render_ring(struct intel_ring_buffer *ring) 
	struct drm_i915_private *dev_priv = dev->dev_private;

	int ret = init_ring_common(ring);



	if (INTEL_INFO(dev)->gen > 3) {

	if (INTEL_INFO(dev)->gen > 3)

		I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));



	/* We need to disable the AsyncFlip performance optimisations in order

	 * to use MI_WAIT_FOR_EVENT within the CS. It should already be

	 * programmed to '1' on all products.

	 */

	if (INTEL_INFO(dev)->gen >= 6)

		I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));



	/* Required for the hardware to program scanline values for waiting */

	if (INTEL_INFO(dev)->gen == 6)

		I915_WRITE(GFX_MODE,

			   _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));



	if (IS_GEN7(dev))

		I915_WRITE(GFX_MODE_GEN7,

			   _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |

			   _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));

	}



	if (INTEL_INFO(dev)->gen >= 5) {

		ret = init_pipe_control(ring);

drivers/iommu/intel-iommu.c

+15 −6
Original line number Diff line number Diff line
@@ -4234,6 +4234,21 @@ static struct iommu_ops intel_iommu_ops = { 
	.pgsize_bitmap	= INTEL_IOMMU_PGSIZES,

};



static void quirk_iommu_g4x_gfx(struct pci_dev *dev)

{

	/* G4x/GM45 integrated gfx dmar support is totally busted. */

	printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n");

	dmar_map_gfx = 0;

}



DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_g4x_gfx);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_g4x_gfx);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_g4x_gfx);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_g4x_gfx);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_g4x_gfx);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_g4x_gfx);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_g4x_gfx);



static void quirk_iommu_rwbf(struct pci_dev *dev)

{

	/*
@@ -4242,12 +4257,6 @@ static void quirk_iommu_rwbf(struct pci_dev *dev) 
	 */

	printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");

	rwbf_quirk = 1;



	/* https://bugzilla.redhat.com/show_bug.cgi?id=538163 */

	if (dev->revision == 0x07) {

		printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n");

		dmar_map_gfx = 0;

	}

}



DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);

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