Commit 482f0e53 authored by Monk Liu's avatar Monk Liu Committed by Alex Deucher
Browse files

drm/amdgpu: fix double ucode load by PSP(v3)



previously the ucode loading of PSP was repreated, one executed in
phase_1 init/re-init/resume and the other in fw_loading routine

Avoid this double loading by clearing ip_blocks.status.hw in suspend or reset
prior to the FW loading and any block's hw_init/resume

v2:
still do the smu fw loading since it is needed by bare-metal

v3:
drop the change in reinit_early_sriov, just clear all block's status.hw
in the head place and set the status.hw after hw_init done is enough

Signed-off-by: default avatarMonk Liu <Monk.Liu@amd.com>
Reviewed-by: default avatarEmily Deng <Emily.Deng@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9244d3a6
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+38 −21
Original line number Diff line number Diff line
@@ -1745,10 +1745,14 @@ static int amdgpu_device_fw_loading(struct amdgpu_device *adev)

	if (adev->asic_type >= CHIP_VEGA10) {
		for (i = 0; i < adev->num_ip_blocks; i++) {
			if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
			if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP)
				continue;

			/* no need to do the fw loading again if already done*/
			if (adev->ip_blocks[i].status.hw == true)
				break;

			if (adev->in_gpu_reset || adev->in_suspend) {
					if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset)
						break; /* sriov gpu reset, psp need to do hw_init before IH because of hw limit */
				r = adev->ip_blocks[i].version->funcs->resume(adev);
				if (r) {
					DRM_ERROR("resume of IP block <%s> failed %d\n",
@@ -1763,10 +1767,12 @@ static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
					return r;
				}
			}

			adev->ip_blocks[i].status.hw = true;
			break;
		}
	}
	}

	r = amdgpu_pm_load_smu_firmware(adev, &smu_version);

	return r;
@@ -2208,7 +2214,9 @@ static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
			if (r) {
				DRM_ERROR("suspend of IP block <%s> failed %d\n",
					  adev->ip_blocks[i].version->funcs->name, r);
				return r;
			}
			adev->ip_blocks[i].status.hw = false;
		}
	}

@@ -2255,7 +2263,9 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
				if (r) {
					DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
						  adev->mp1_state, r);
					return r;
				}
				adev->ip_blocks[i].status.hw = false;
			}
		}
	}
@@ -2310,6 +2320,7 @@ static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
		for (j = 0; j < adev->num_ip_blocks; j++) {
			block = &adev->ip_blocks[j];

			block->status.hw = false;
			if (block->version->type != ip_order[i] ||
				!block->status.valid)
				continue;
@@ -2318,6 +2329,7 @@ static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
			DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
			if (r)
				return r;
			block->status.hw = true;
		}
	}

@@ -2345,13 +2357,15 @@ static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
			block = &adev->ip_blocks[j];

			if (block->version->type != ip_order[i] ||
				!block->status.valid)
				!block->status.valid ||
				block->status.hw)
				continue;

			r = block->version->funcs->hw_init(adev);
			DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
			if (r)
				return r;
			block->status.hw = true;
		}
	}

@@ -2375,17 +2389,19 @@ static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
	int i, r;

	for (i = 0; i < adev->num_ip_blocks; i++) {
		if (!adev->ip_blocks[i].status.valid)
		if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
			continue;
		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
		    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
		    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {

			r = adev->ip_blocks[i].version->funcs->resume(adev);
			if (r) {
				DRM_ERROR("resume of IP block <%s> failed %d\n",
					  adev->ip_blocks[i].version->funcs->name, r);
				return r;
			}
			adev->ip_blocks[i].status.hw = true;
		}
	}

@@ -2410,7 +2426,7 @@ static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
	int i, r;

	for (i = 0; i < adev->num_ip_blocks; i++) {
		if (!adev->ip_blocks[i].status.valid)
		if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
			continue;
		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
		    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
@@ -2423,6 +2439,7 @@ static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
				  adev->ip_blocks[i].version->funcs->name, r);
			return r;
		}
		adev->ip_blocks[i].status.hw = true;
	}

	return 0;