Commit 48016851 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2013-09-06' of... 

Merge tag 'drm-intel-fixes-2013-09-06' of git://people.freedesktop.org/~danvet/drm-intel into drm-fixes

- Early stolen mem reservation from Jesse in x86 boot code. Acked by Ingo
  and hpa.  This was ready much earlier but somehow I've thought it'd go
  in through x86 trees, hence why this is late. Avoids the pci resource
  code to plant mmiobars in the middle of stolen mem and other ugliness.
- vgaarb improvements from Alex Williamson plus the fix from Ville for the
  vgacon->fbcon smooth transition "feature".
- Render pageflips on ivb/hsw to avoid stalls due to the ring switching
  when only flipping on the blitter (Chris).
- Deadlock fixes around our flush_workqueue which crept back in - lockdep
  isn't clever enough :(
- Shrinker recursion fix from Chris - this is the thing that blew the vma
  patches from Ben I've taken out of 3.12.
- Fixup for the relocation refactoring. Also an igt testcase to make sure
  we don't break this again.
- Pile of smaller fixups all over, shortlog has full details.

* tag 'drm-intel-fixes-2013-09-06' of git://people.freedesktop.org/~danvet/drm-intel: (29 commits)
  drm/i915: Delay disabling of VGA memory until vgacon->fbcon handoff is done
  drm/i915: try not to lose backlight CBLV precision
  drm/i915: Confine page flips to BCS on Valleyview
  drm/i915: Skip stolen region initialisation if none is reserved
  drm/i915: fix gpu hang vs. flip stall deadlocks
  drm/i915: Hold an object reference whilst we shrink it
  drm/i915: fix i9xx_crtc_clock_get for multiplied pixels
  drm/i915: handle sdvo input pixel multiplier correctly again
  drm/i915: fix hpd work vs. flush_work in the pageflip code deadlock
  drm/i915: fix up the relocate_entry refactoring
  drm/i915: Fix pipe config warnings when dealing with LVDS fixed mode
  drm/i915: Don't call sg_free_table() if sg_alloc_table() fails
  i915: Update VGA arbiter support for newer devices
  vgaarb: Fix VGA decodes changes
  vgaarb: Don't disable resources that are not owned
  drm/i915: Pin pages whilst mapping the dma-buf
  drm/i915: enable trickle feed on Haswell
  x86: add early quirk for reserving Intel graphics stolen memory v5
  drm/i915: split PCI IDs out into i915_drm.h v4
  i915_gem: Convert kmem_cache_alloc(...GFP_ZERO) to kmem_cache_zalloc
  ...
parents 86a7e122 6e1b4fda

arch/x86/kernel/early-quirks.c

+154 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
#include <linux/pci.h>

#include <linux/acpi.h>

#include <linux/pci_ids.h>

#include <drm/i915_drm.h>

#include <asm/pci-direct.h>

#include <asm/dma.h>

#include <asm/io_apic.h>
@@ -216,6 +217,157 @@ static void __init intel_remapping_check(int num, int slot, int func) 


}



/*

 * Systems with Intel graphics controllers set aside memory exclusively

 * for gfx driver use.  This memory is not marked in the E820 as reserved

 * or as RAM, and so is subject to overlap from E820 manipulation later

 * in the boot process.  On some systems, MMIO space is allocated on top,

 * despite the efforts of the "RAM buffer" approach, which simply rounds

 * memory boundaries up to 64M to try to catch space that may decode

 * as RAM and so is not suitable for MMIO.

 *

 * And yes, so far on current devices the base addr is always under 4G.

 */

static u32 __init intel_stolen_base(int num, int slot, int func)

{

	u32 base;



	/*

	 * For the PCI IDs in this quirk, the stolen base is always

	 * in 0x5c, aka the BDSM register (yes that's really what

	 * it's called).

	 */

	base = read_pci_config(num, slot, func, 0x5c);

	base &= ~((1<<20) - 1);



	return base;

}



#define KB(x)	((x) * 1024)

#define MB(x)	(KB (KB (x)))

#define GB(x)	(MB (KB (x)))



static size_t __init gen3_stolen_size(int num, int slot, int func)

{

	size_t stolen_size;

	u16 gmch_ctrl;



	gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);



	switch (gmch_ctrl & I855_GMCH_GMS_MASK) {

	case I855_GMCH_GMS_STOLEN_1M:

		stolen_size = MB(1);

		break;

	case I855_GMCH_GMS_STOLEN_4M:

		stolen_size = MB(4);

		break;

	case I855_GMCH_GMS_STOLEN_8M:

		stolen_size = MB(8);

		break;

	case I855_GMCH_GMS_STOLEN_16M:

		stolen_size = MB(16);

		break;

	case I855_GMCH_GMS_STOLEN_32M:

		stolen_size = MB(32);

		break;

	case I915_GMCH_GMS_STOLEN_48M:

		stolen_size = MB(48);

		break;

	case I915_GMCH_GMS_STOLEN_64M:

		stolen_size = MB(64);

		break;

	case G33_GMCH_GMS_STOLEN_128M:

		stolen_size = MB(128);

		break;

	case G33_GMCH_GMS_STOLEN_256M:

		stolen_size = MB(256);

		break;

	case INTEL_GMCH_GMS_STOLEN_96M:

		stolen_size = MB(96);

		break;

	case INTEL_GMCH_GMS_STOLEN_160M:

		stolen_size = MB(160);

		break;

	case INTEL_GMCH_GMS_STOLEN_224M:

		stolen_size = MB(224);

		break;

	case INTEL_GMCH_GMS_STOLEN_352M:

		stolen_size = MB(352);

		break;

	default:

		stolen_size = 0;

		break;

	}



	return stolen_size;

}



static size_t __init gen6_stolen_size(int num, int slot, int func)

{

	u16 gmch_ctrl;



	gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);

	gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;

	gmch_ctrl &= SNB_GMCH_GMS_MASK;



	return gmch_ctrl << 25; /* 32 MB units */

}



typedef size_t (*stolen_size_fn)(int num, int slot, int func);



static struct pci_device_id intel_stolen_ids[] __initdata = {

	INTEL_I915G_IDS(gen3_stolen_size),

	INTEL_I915GM_IDS(gen3_stolen_size),

	INTEL_I945G_IDS(gen3_stolen_size),

	INTEL_I945GM_IDS(gen3_stolen_size),

	INTEL_VLV_M_IDS(gen3_stolen_size),

	INTEL_VLV_D_IDS(gen3_stolen_size),

	INTEL_PINEVIEW_IDS(gen3_stolen_size),

	INTEL_I965G_IDS(gen3_stolen_size),

	INTEL_G33_IDS(gen3_stolen_size),

	INTEL_I965GM_IDS(gen3_stolen_size),

	INTEL_GM45_IDS(gen3_stolen_size),

	INTEL_G45_IDS(gen3_stolen_size),

	INTEL_IRONLAKE_D_IDS(gen3_stolen_size),

	INTEL_IRONLAKE_M_IDS(gen3_stolen_size),

	INTEL_SNB_D_IDS(gen6_stolen_size),

	INTEL_SNB_M_IDS(gen6_stolen_size),

	INTEL_IVB_M_IDS(gen6_stolen_size),

	INTEL_IVB_D_IDS(gen6_stolen_size),

	INTEL_HSW_D_IDS(gen6_stolen_size),

	INTEL_HSW_M_IDS(gen6_stolen_size),

};



static void __init intel_graphics_stolen(int num, int slot, int func)

{

	size_t size;

	int i;

	u32 start;

	u16 device, subvendor, subdevice;



	device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);

	subvendor = read_pci_config_16(num, slot, func,

				       PCI_SUBSYSTEM_VENDOR_ID);

	subdevice = read_pci_config_16(num, slot, func, PCI_SUBSYSTEM_ID);



	for (i = 0; i < ARRAY_SIZE(intel_stolen_ids); i++) {

		if (intel_stolen_ids[i].device == device) {

			stolen_size_fn stolen_size =

				(stolen_size_fn)intel_stolen_ids[i].driver_data;

			size = stolen_size(num, slot, func);

			start = intel_stolen_base(num, slot, func);

			if (size && start) {

				/* Mark this space as reserved */

				e820_add_region(start, size, E820_RESERVED);

				sanitize_e820_map(e820.map,

						  ARRAY_SIZE(e820.map),

						  &e820.nr_map);

			}

			return;

		}

	}

}



#define QFLAG_APPLY_ONCE 	0x1

#define QFLAG_APPLIED		0x2

#define QFLAG_DONE		(QFLAG_APPLY_ONCE|QFLAG_APPLIED)
@@ -251,6 +403,8 @@ static struct chipset early_qrk[] __initdata = { 
	  PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },

	{ PCI_VENDOR_ID_INTEL, 0x3406, PCI_CLASS_BRIDGE_HOST,

	  PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },

	{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, PCI_ANY_ID,

	  QFLAG_APPLY_ONCE, intel_graphics_stolen },

	{}

};

drivers/gpu/drm/i915/i915_debugfs.c

+10 −1
Original line number Diff line number Diff line
@@ -857,7 +857,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused) 
		u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);

		u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);

		u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);

		u32 rpstat, cagf;

		u32 rpstat, cagf, reqf;

		u32 rpupei, rpcurup, rpprevup;

		u32 rpdownei, rpcurdown, rpprevdown;

		int max_freq;
@@ -869,6 +869,14 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused) 


		gen6_gt_force_wake_get(dev_priv);



		reqf = I915_READ(GEN6_RPNSWREQ);

		reqf &= ~GEN6_TURBO_DISABLE;

		if (IS_HASWELL(dev))

			reqf >>= 24;

		else

			reqf >>= 25;

		reqf *= GT_FREQUENCY_MULTIPLIER;



		rpstat = I915_READ(GEN6_RPSTAT1);

		rpupei = I915_READ(GEN6_RP_CUR_UP_EI);

		rpcurup = I915_READ(GEN6_RP_CUR_UP);
@@ -893,6 +901,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused) 
			   gt_perf_status & 0xff);

		seq_printf(m, "Render p-state limit: %d\n",

			   rp_state_limits & 0xff);

		seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);

		seq_printf(m, "CAGF: %dMHz\n", cagf);

		seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &

			   GEN6_CURICONT_MASK);

drivers/gpu/drm/i915/i915_dma.c

+12 −3
Original line number Diff line number Diff line
@@ -1290,9 +1290,12 @@ static int i915_load_modeset_init(struct drm_device *dev) 
	 * then we do not take part in VGA arbitration and the

	 * vga_client_register() fails with -ENODEV.

	 */

	ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);

	if (!HAS_PCH_SPLIT(dev)) {

		ret = vga_client_register(dev->pdev, dev, NULL,

					  i915_vga_set_decode);

		if (ret && ret != -ENODEV)

			goto out;

	}



	intel_register_dsm_handler();
@@ -1348,6 +1351,12 @@ static int i915_load_modeset_init(struct drm_device *dev) 
	 */

	intel_fbdev_initial_config(dev);



	/*

	 * Must do this after fbcon init so that

	 * vgacon_save_screen() works during the handover.

	 */

	i915_disable_vga_mem(dev);



	/* Only enable hotplug handling once the fbdev is fully set up. */

	dev_priv->enable_hotplug_processing = true;

drivers/gpu/drm/i915/i915_drv.c

+34 −130
Original line number Diff line number Diff line
@@ -157,25 +157,6 @@ MODULE_PARM_DESC(prefault_disable, 
static struct drm_driver driver;

extern int intel_agp_enabled;



#define INTEL_VGA_DEVICE(id, info) {		\

	.class = PCI_BASE_CLASS_DISPLAY << 16,	\

	.class_mask = 0xff0000,			\

	.vendor = 0x8086,			\

	.device = id,				\

	.subvendor = PCI_ANY_ID,		\

	.subdevice = PCI_ANY_ID,		\

	.driver_data = (unsigned long) info }



#define INTEL_QUANTA_VGA_DEVICE(info) {		\

	.class = PCI_BASE_CLASS_DISPLAY << 16,	\

	.class_mask = 0xff0000,			\

	.vendor = 0x8086,			\

	.device = 0x16a,			\

	.subvendor = 0x152d,			\

	.subdevice = 0x8990,			\

	.driver_data = (unsigned long) info }





static const struct intel_device_info intel_i830_info = {

	.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,

	.has_overlay = 1, .overlay_needs_physical = 1,
@@ -350,118 +331,41 @@ static const struct intel_device_info intel_haswell_m_info = { 
	.has_vebox_ring = 1,

};



/*

 * Make sure any device matches here are from most specific to most

 * general.  For example, since the Quanta match is based on the subsystem

 * and subvendor IDs, we need it to come before the more general IVB

 * PCI ID matches, otherwise we'll use the wrong info struct above.

 */

#define INTEL_PCI_IDS \

	INTEL_I830_IDS(&intel_i830_info),	\

	INTEL_I845G_IDS(&intel_845g_info),	\

	INTEL_I85X_IDS(&intel_i85x_info),	\

	INTEL_I865G_IDS(&intel_i865g_info),	\

	INTEL_I915G_IDS(&intel_i915g_info),	\

	INTEL_I915GM_IDS(&intel_i915gm_info),	\

	INTEL_I945G_IDS(&intel_i945g_info),	\

	INTEL_I945GM_IDS(&intel_i945gm_info),	\

	INTEL_I965G_IDS(&intel_i965g_info),	\

	INTEL_G33_IDS(&intel_g33_info),		\

	INTEL_I965GM_IDS(&intel_i965gm_info),	\

	INTEL_GM45_IDS(&intel_gm45_info), 	\

	INTEL_G45_IDS(&intel_g45_info), 	\

	INTEL_PINEVIEW_IDS(&intel_pineview_info),	\

	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),	\

	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),	\

	INTEL_SNB_D_IDS(&intel_sandybridge_d_info),	\

	INTEL_SNB_M_IDS(&intel_sandybridge_m_info),	\

	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \

	INTEL_IVB_M_IDS(&intel_ivybridge_m_info),	\

	INTEL_IVB_D_IDS(&intel_ivybridge_d_info),	\

	INTEL_HSW_D_IDS(&intel_haswell_d_info), \

	INTEL_HSW_M_IDS(&intel_haswell_m_info), \

	INTEL_VLV_M_IDS(&intel_valleyview_m_info),	\

	INTEL_VLV_D_IDS(&intel_valleyview_d_info)



static const struct pci_device_id pciidlist[] = {		/* aka */

	INTEL_VGA_DEVICE(0x3577, &intel_i830_info),		/* I830_M */

	INTEL_VGA_DEVICE(0x2562, &intel_845g_info),		/* 845_G */

	INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),		/* I855_GM */

	INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),

	INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),		/* I865_G */

	INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),		/* I915_G */

	INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),		/* E7221_G */

	INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),		/* I915_GM */

	INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),		/* I945_G */

	INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),		/* I945_GM */

	INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),		/* I945_GME */

	INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),		/* I946_GZ */

	INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),		/* G35_G */

	INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),		/* I965_Q */

	INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),		/* I965_G */

	INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),		/* Q35_G */

	INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),		/* G33_G */

	INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),		/* Q33_G */

	INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),		/* I965_GM */

	INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),		/* I965_GME */

	INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),		/* GM45_G */

	INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),		/* IGD_E_G */

	INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),		/* Q45_G */

	INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),		/* G45_G */

	INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),		/* G41_G */

	INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),		/* B43_G */

	INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),		/* B43_G.1 */

	INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),

	INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),

	INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),

	INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),

	INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),

	INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),

	INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),

	INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),

	INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),

	INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),

	INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),

	INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */

	INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */

	INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */

	INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */

	INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */

	INTEL_QUANTA_VGA_DEVICE(&intel_ivybridge_q_info), /* Quanta transcode */

	INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */

	INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */

	INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */

	INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT3 desktop */

	INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */

	INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */

	INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT3 server */

	INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */

	INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */

	INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */

	INTEL_VGA_DEVICE(0x040B, &intel_haswell_d_info), /* GT1 reserved */

	INTEL_VGA_DEVICE(0x041B, &intel_haswell_d_info), /* GT2 reserved */

	INTEL_VGA_DEVICE(0x042B, &intel_haswell_d_info), /* GT3 reserved */

	INTEL_VGA_DEVICE(0x040E, &intel_haswell_d_info), /* GT1 reserved */

	INTEL_VGA_DEVICE(0x041E, &intel_haswell_d_info), /* GT2 reserved */

	INTEL_VGA_DEVICE(0x042E, &intel_haswell_d_info), /* GT3 reserved */

	INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */

	INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */

	INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT3 desktop */

	INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */

	INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */

	INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT3 server */

	INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */

	INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */

	INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT3 mobile */

	INTEL_VGA_DEVICE(0x0C0B, &intel_haswell_d_info), /* SDV GT1 reserved */

	INTEL_VGA_DEVICE(0x0C1B, &intel_haswell_d_info), /* SDV GT2 reserved */

	INTEL_VGA_DEVICE(0x0C2B, &intel_haswell_d_info), /* SDV GT3 reserved */

	INTEL_VGA_DEVICE(0x0C0E, &intel_haswell_d_info), /* SDV GT1 reserved */

	INTEL_VGA_DEVICE(0x0C1E, &intel_haswell_d_info), /* SDV GT2 reserved */

	INTEL_VGA_DEVICE(0x0C2E, &intel_haswell_d_info), /* SDV GT3 reserved */

	INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */

	INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */

	INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT3 desktop */

	INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */

	INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */

	INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT3 server */

	INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */

	INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */

	INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT3 mobile */

	INTEL_VGA_DEVICE(0x0A0B, &intel_haswell_d_info), /* ULT GT1 reserved */

	INTEL_VGA_DEVICE(0x0A1B, &intel_haswell_d_info), /* ULT GT2 reserved */

	INTEL_VGA_DEVICE(0x0A2B, &intel_haswell_d_info), /* ULT GT3 reserved */

	INTEL_VGA_DEVICE(0x0A0E, &intel_haswell_m_info), /* ULT GT1 reserved */

	INTEL_VGA_DEVICE(0x0A1E, &intel_haswell_m_info), /* ULT GT2 reserved */

	INTEL_VGA_DEVICE(0x0A2E, &intel_haswell_m_info), /* ULT GT3 reserved */

	INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */

	INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */

	INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT3 desktop */

	INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */

	INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */

	INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT3 server */

	INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */

	INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */

	INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT3 mobile */

	INTEL_VGA_DEVICE(0x0D0B, &intel_haswell_d_info), /* CRW GT1 reserved */

	INTEL_VGA_DEVICE(0x0D1B, &intel_haswell_d_info), /* CRW GT2 reserved */

	INTEL_VGA_DEVICE(0x0D2B, &intel_haswell_d_info), /* CRW GT3 reserved */

	INTEL_VGA_DEVICE(0x0D0E, &intel_haswell_d_info), /* CRW GT1 reserved */

	INTEL_VGA_DEVICE(0x0D1E, &intel_haswell_d_info), /* CRW GT2 reserved */

	INTEL_VGA_DEVICE(0x0D2E, &intel_haswell_d_info), /* CRW GT3 reserved */

	INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),

	INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info),

	INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info),

	INTEL_VGA_DEVICE(0x0f33, &intel_valleyview_m_info),

	INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),

	INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),

	INTEL_PCI_IDS,

	{0, 0, 0}

};

drivers/gpu/drm/i915/i915_drv.h

+7 −0
Original line number Diff line number Diff line
@@ -1236,6 +1236,13 @@ typedef struct drm_i915_private { 


	unsigned int fsb_freq, mem_freq, is_ddr3;



	/**

	 * wq - Driver workqueue for GEM.

	 *

	 * NOTE: Work items scheduled here are not allowed to grab any modeset

	 * locks, for otherwise the flushing done in the pageflip code will

	 * result in deadlocks.

	 */

	struct workqueue_struct *wq;



	/* Display functions */

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