Merge tag 'dmaengine-5.3-rc1' of git://git.infradead.org/users/vkoul/slave-dma

  - dma-channels: contains the total number of DMA channels supported by the DMAC

  - dma-requests: contains the total number of DMA requests supported by the DMAC

  - arm,pl330-broken-no-flushp: quirk for avoiding to execute DMAFLUSHP

  - resets: contains an entry for each entry in reset-names.

	    See ../reset/reset.txt for details.

  - reset-names: must contain at least "dma", and optional is "dma-ocp".

Example:

Required properties:

- compatible :

	- "fsl,vf610-edma" for eDMA used similar to that on Vybrid vf610 SoC

	- "fsl,imx7ulp-edma" for eDMA2 used similar to that on i.mx7ulp

- reg : Specifies base physical address(s) and size of the eDMA registers.

	The 1st region is eDMA control register's address and size.

	The 2nd and the 3rd regions are programmable channel multiplexing

	control register's address and size.

- interrupts : A list of interrupt-specifiers, one for each entry in

	interrupt-names.

- interrupt-names : Should contain:

	"edma-tx" - the transmission interrupt

	"edma-err" - the error interrupt

	interrupt-names on vf610 similar SoC. But for i.mx7ulp per channel

	per transmission interrupt, total 16 channel interrupt and 1

	error interrupt(located in the last), no interrupt-names list on

	i.mx7ulp for clean on dts.

- #dma-cells : Must be <2>.

	The 1st cell specifies the DMAMUX(0 for DMAMUX0 and 1 for DMAMUX1).

	Specific request source can only be multiplexed by specific channels

- clock-names : A list of channel group clock names. Should contain:

	"dmamux0" - clock name of mux0 group

	"dmamux1" - clock name of mux1 group

	Note: No dmamux0 on i.mx7ulp, but another 'dma' clk added on i.mx7ulp.

- clocks : A list of phandle and clock-specifier pairs, one for each entry in

	clock-names.

- big-endian: If present registers and hardware scatter/gather descriptors

	of the eDMA are implemented in big endian mode, otherwise in little

	mode.

- interrupt-names : Should contain the below on vf610 similar SoC but not used

	on i.mx7ulp similar SoC:

	"edma-tx" - the transmission interrupt

	"edma-err" - the error interrupt

Examples:

	clock-names = "dmamux0", "dmamux1";

	clocks = <&clks VF610_CLK_DMAMUX0>,

		<&clks VF610_CLK_DMAMUX1>;

};

}; /* vf610 */

edma1: dma-controller@40080000 {

	#dma-cells = <2>;

	compatible = "fsl,imx7ulp-edma";

	reg = <0x40080000 0x2000>,

		<0x40210000 0x1000>;

	dma-channels = <32>;

	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,

		     /* last is eDMA2-ERR interrupt */

		     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;

	clock-names = "dma", "dmamux0";

	clocks = <&pcc2 IMX7ULP_CLK_DMA1>,

		 <&pcc2 IMX7ULP_CLK_DMA_MUX1>;

}; /* i.mx7ulp */

* DMA clients

DMA client drivers that uses the DMA function must use the format described

- reg: The base address of the APDMA register bank.

- interrupts: A single interrupt specifier.

 One interrupt per dma-requests, or 8 if no dma-requests property is present

- dma-requests: The number of DMA channels

- clocks : Must contain an entry for each entry in clock-names.

  See ../clocks/clock-bindings.txt for details.

- clock-names: The APDMA clock for register accesses

- mediatek,dma-33bits: Present if the DMA requires support

Examples:

	apdma: dma-controller@11000380 {

	apdma: dma-controller@11000400 {

		compatible = "mediatek,mt2712-uart-dma";

		reg = <0 0x11000380 0 0x400>;

		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 65 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 66 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 68 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 69 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;

		reg = <0 0x11000400 0 0x80>,

		      <0 0x11000480 0 0x80>,

		      <0 0x11000500 0 0x80>,

		      <0 0x11000580 0 0x80>,

		      <0 0x11000600 0 0x80>,

		      <0 0x11000680 0 0x80>,

		      <0 0x11000700 0 0x80>,

		      <0 0x11000780 0 0x80>,

		      <0 0x11000800 0 0x80>,

		      <0 0x11000880 0 0x80>,

		      <0 0x11000900 0 0x80>,

		      <0 0x11000980 0 0x80>;

		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;

		dma-requests = <12>;

		clocks = <&pericfg CLK_PERI_AP_DMA>;

		clock-names = "apdma";

		mediatek,dma-33bits;

		#dma-cells = <1>;

	};

	};

------------------------------------------------------------------------------

For A64 DMA controller:

For A64 and H6 DMA controller:

Required properties:

- compatible:	"allwinner,sun50i-a64-dma"

- compatible:	Must be one of

		  "allwinner,sun50i-a64-dma"

		  "allwinner,sun50i-h6-dma"

- dma-channels: Number of DMA channels supported by the controller.

		Refer to Documentation/devicetree/bindings/dma/dma.txt

- clocks:	In addition to parent AHB clock, it should also contain mbus

		clock (H6 only)

- clock-names:	Should contain "bus" and "mbus" (H6 only)

- all properties above, i.e. reg, interrupts, clocks, resets and #dma-cells

Optional properties:

    dmatest.timeout=2000 dmatest.iterations=1 dmatest.channel=dma0chan0 dmatest.run=1

Example of multi-channel test usage:

Example of multi-channel test usage (new in the 5.0 kernel)::

    % modprobe dmatest

    % echo 2000 > /sys/module/dmatest/parameters/timeout

    % echo 1 > /sys/module/dmatest/parameters/iterations

    % echo dma0chan2 > /sys/module/dmatest/parameters/channel

    % echo 1 > /sys/module/dmatest/parameters/run

Note: the channel parameter should always be the last parameter set prior to

running the test (setting run=1), this is because upon setting the channel

parameter, that specific channel is requested using the dmaengine and a thread

is created with the existing parameters. This thread is set as pending

and will be executed once run is set to 1. Any parameters set after the thread

is created are not applied.

.. note::

  For all tests, starting in the 5.0 kernel, either single- or multi-channel,

  the channel parameter(s) must be set after all other parameters. It is at

  that time that the existing parameter values are acquired for use by the

  thread(s). All other parameters are shared. Therefore, if changes are made

  to any of the other parameters, and an additional channel specified, the

  (shared) parameters used for all threads will use the new values.

  After the channels are specified, each thread is set as pending. All threads

  begin execution when the run parameter is set to 1.

.. hint::

  available channel list could be extracted by running the following command::

  A list of available channels can be found by running the following command::

    % ls -1 /sys/class/dma/

Channels can be freed by setting run to 0.

Example::

    % echo dma0chan1 > /sys/module/dmatest/parameters/channel

    dmatest: Added 1 threads using dma0chan1

    % cat /sys/class/dma/dma0chan1/in_use