mlxsw: reg: Increase trap identifier to 10 bits (47e4b162) · Commits · 戴 / test

The trap identifier was increased to 10 bits in new versions of the Programmer's Reference Manual (PRM). Increase it accordingly in the Host PacKet Trap (HPKT) register and in the Completion Queue Element (CQE). This is significant for subsequent patches that will introduce trap identifiers which utilize the extended range. Signed-off-by:

Amit Cohen <amitc@mellanox.com> Reviewed-by:

Jiri Pirko <jiri@mellanox.com> Signed-off-by:

Petr Machata <petrm@mellanox.com> Signed-off-by:

Ido Schimmel <idosch@mellanox.com> Signed-off-by:

David S. Miller <davem@davemloft.net>

drivers/net/ethernet/mellanox/mlxsw/pci_hw.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -176,7 +176,7 @@ MLXSW_ITEM32(pci, cqe, byte_count, 0x04, 0, 14);
		/* pci_cqe_trap_id
		* Trap ID that captured the packet.
		*/
		MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 9);
		MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 10);

		/* pci_cqe_crc
		* Length include CRC. Indicates the length field includes

drivers/net/ethernet/mellanox/mlxsw/reg.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -5778,7 +5778,7 @@ MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);
		* Note: A trap ID can only be associated with a single trap group. The device
		* will associate the trap ID with the last trap group configured.
		*/
		MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9);
		MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 10);

		enum {
		MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT,

drivers/net/ethernet/mellanox/mlxsw/trap.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -108,7 +108,7 @@ enum {
		MLXSW_TRAP_ID_DISCARD_INGRESS_ACL = 0x1C3,
		MLXSW_TRAP_ID_DISCARD_EGRESS_ACL = 0x1C4,

		MLXSW_TRAP_ID_MAX = 0x1FF
		MLXSW_TRAP_ID_MAX = 0x3FF,
		};

		enum mlxsw_event_trap_id {

Admin message