x86/fpu: Clean up asm/fpu/types.h (47bc5106) · Commits · 戴 / test

- add header guards - standardize vertical alignment - add comments about MPX No code changed. Reviewed-by:

Borislav Petkov <bp@alien8.de> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Oleg Nesterov <oleg@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by:

Ingo Molnar <mingo@kernel.org>

arch/x86/include/asm/fpu/types.h

+30 −20

Original line number	Diff line number	Diff line
		/*
		* FPU data structures:
		*/
		#ifndef _ASM_X86_FPU_H
		#define _ASM_X86_FPU_H

		#define MXCSR_DEFAULT 0x1f80

		@@ -52,6 +57,9 @@ struct i387_fxsave_struct {

		} __attribute__((aligned(16)));

		/*
		* Software based FPU emulation state:
		*/
		struct i387_soft_struct {
		u32 cwd;
		u32 swd;
		@@ -82,6 +90,7 @@ struct lwp_struct {
		u8 reserved[128];
		};

		/* Intel MPX support: */
		struct bndreg {
		u64 lower_bound;
		u64 upper_bound;
		@@ -105,7 +114,7 @@ struct xsave_struct {
		struct lwp_struct lwp;
		struct bndreg bndreg[4];
		struct bndcsr bndcsr;
		/* new processor state extensions will go here */
		/* New processor state extensions will go here. */
		} __attribute__ ((packed, aligned (64)));

		union thread_xstate {
		@@ -130,3 +139,4 @@ struct fpu {
		unsigned char counter;
		};

		#endif /* _ASM_X86_FPU_H */

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