Commit 477d7cae authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'mailbox-for-next' of git://git.linaro.org/landing-teams/working/fujitsu/integration 

Pull mailbox updates from Jassi Brar:

 - new driver for Broadcom FlexRM controller

 - constify data structures of callback functions in some drivers

 - a few bug fixes uncovered by multi-threaded use of mailbox channels
   in blocking mode

* 'mailbox-for-next' of git://git.linaro.org/landing-teams/working/fujitsu/integration:
  mailbox: handle empty message in tx_tick
  mailbox: skip complete wait event if timer expired
  mailbox: always wait in mbox_send_message for blocking Tx mode
  mailbox: Remove depends on COMPILE_TEST for BCM_FLEXRM_MBOX
  mailbox: check ->last_tx_done for NULL in case of timer-based polling
  dt-bindings: Add DT bindings info for FlexRM ring manager
  mailbox: Add driver for Broadcom FlexRM ring manager
  dt-bindings: mailbox: Update doc with NSP PDC/mailbox support
  mailbox: bcm-pdc: Add Northstar Plus support to PDC driver
  mailbox: constify mbox_chan_ops structures
parents 6fb41cbd cb710ab1

Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.txt

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Broadcom FlexRM Ring Manager

============================

The Broadcom FlexRM ring manager provides a set of rings which can be

used to submit work to offload engines. An SoC may have multiple FlexRM

hardware blocks. There is one device tree entry per FlexRM block. The

FlexRM driver will create a mailbox-controller instance for given FlexRM

hardware block where each mailbox channel is a separate FlexRM ring.



Required properties:

--------------------

- compatible:	Should be "brcm,iproc-flexrm-mbox"

- reg:		Specifies base physical address and size of the FlexRM

		ring registers

- msi-parent:	Phandles (and potential Device IDs) to MSI controllers

		The FlexRM engine will send MSIs (instead of wired

		interrupts) to CPU. There is one MSI for each FlexRM ring.

		Refer devicetree/bindings/interrupt-controller/msi.txt

- #mbox-cells:	Specifies the number of cells needed to encode a mailbox

		channel. This should be 3.



		The 1st cell is the mailbox channel number.



		The 2nd cell contains MSI completion threshold. This is the

		number of completion messages for which FlexRM will inject

		one MSI interrupt to CPU.



		The 3nd cell contains MSI timer value representing time for

		which FlexRM will wait to accumulate N completion messages

		where N is the value specified by 2nd cell above. If FlexRM

		does not get required number of completion messages in time

		specified by this cell then it will inject one MSI interrupt

		to CPU provided atleast one completion message is available.



Optional properties:

--------------------

- dma-coherent:	Present if DMA operations made by the FlexRM engine (such

		as DMA descriptor access, access to buffers pointed by DMA

		descriptors and read/write pointer updates to DDR) are

		cache coherent with the CPU.



Example:

--------

crypto_mbox: mbox@67000000 {

	compatible = "brcm,iproc-flexrm-mbox";

	reg = <0x67000000 0x200000>;

	msi-parent = <&gic_its 0x7f00>;

	#mbox-cells = <3>;

};



crypto@672c0000 {

	compatible = "brcm,spu2-v2-crypto";

	reg = <0x672c0000 0x1000>;

	mboxes = <&crypto_mbox 0 0x1 0xffff>,

		 <&crypto_mbox 1 0x1 0xffff>,

		 <&crypto_mbox 16 0x1 0xffff>,

		 <&crypto_mbox 17 0x1 0xffff>,

		 <&crypto_mbox 30 0x1 0xffff>,

		 <&crypto_mbox 31 0x1 0xffff>;

};

Documentation/devicetree/bindings/mailbox/brcm,iproc-pdc-mbox.txt

+4 −2
Original line number Original line Diff line number Diff line 
The PDC driver manages data transfer to and from various offload engines

The PDC driver manages data transfer to and from various offload engines

on some Broadcom SoCs. An SoC may have multiple PDC hardware blocks. There is

on some Broadcom SoCs. An SoC may have multiple PDC hardware blocks. There is

one device tree entry per block.

one device tree entry per block.  On some chips, the PDC functionality is

handled by the FA2 (Northstar Plus).





Required properties:

Required properties:

- compatible : Should be "brcm,iproc-pdc-mbox".

- compatible : Should be "brcm,iproc-pdc-mbox" or "brcm,iproc-fa2-mbox" for

  FA2/Northstar Plus.

- reg: Should contain PDC registers location and length.

- reg: Should contain PDC registers location and length.

- interrupts: Should contain the IRQ line for the PDC.

- interrupts: Should contain the IRQ line for the PDC.

- #mbox-cells: 1

- #mbox-cells: 1

drivers/mailbox/Kconfig

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@@ -144,12 +144,22 @@ config XGENE_SLIMPRO_MBOX 
	  want to use the APM X-Gene SLIMpro IPCM support.

	  want to use the APM X-Gene SLIMpro IPCM support.





config BCM_PDC_MBOX

config BCM_PDC_MBOX

	tristate "Broadcom PDC Mailbox"

	tristate "Broadcom FlexSparx DMA Mailbox"

	depends on ARM64 || COMPILE_TEST

	depends on ARCH_BCM_IPROC || COMPILE_TEST

	depends on HAS_DMA

	depends on HAS_DMA

	help

	  Mailbox implementation for the Broadcom FlexSparx DMA ring manager,

	  which provides access to various offload engines on Broadcom

	  SoCs, including FA2/FA+ on Northstar Plus and PDC on Northstar 2.



config BCM_FLEXRM_MBOX

	tristate "Broadcom FlexRM Mailbox"

	depends on ARM64

	depends on HAS_DMA

	select GENERIC_MSI_IRQ_DOMAIN

	default ARCH_BCM_IPROC

	default ARCH_BCM_IPROC

	help

	help

	  Mailbox implementation for the Broadcom PDC ring manager,

	  Mailbox implementation of the Broadcom FlexRM ring manager,

	  which provides access to various offload engines on Broadcom

	  which provides access to various offload engines on Broadcom

	  SoCs. Say Y here if you want to use the Broadcom PDC.

	  SoCs. Say Y here if you want to use the Broadcom FlexRM.

endif
 
endif

drivers/mailbox/Makefile

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@@ -30,4 +30,6 @@ obj-$(CONFIG_HI6220_MBOX) += hi6220-mailbox.o 




obj-$(CONFIG_BCM_PDC_MBOX)	+= bcm-pdc-mailbox.o

obj-$(CONFIG_BCM_PDC_MBOX)	+= bcm-pdc-mailbox.o





obj-$(CONFIG_BCM_FLEXRM_MBOX)	+= bcm-flexrm-mailbox.o



obj-$(CONFIG_TEGRA_HSP_MBOX)	+= tegra-hsp.o
 
obj-$(CONFIG_TEGRA_HSP_MBOX)	+= tegra-hsp.o

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