Commit 47734f89 authored by Ingo Molnar's avatar Ingo Molnar
Browse files

sched: Clean up topology.h 



Re-organize the flag settings so that it's visible at a glance
which sched-domains flags are set and which not.

With the new balancer code we'll need to re-tune these details
anyway, so make it cleaner to make fewer mistakes down the
road ;-)

Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Andreas Herrmann <andreas.herrmann3@amd.com>
Cc: Andreas Herrmann <andreas.herrmann3@amd.com>
Cc: Gautham R Shenoy <ego@in.ibm.com>
Cc: Balbir Singh <balbir@in.ibm.com>
LKML-Reference: <new-submission>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent d7ea17a7

arch/x86/include/asm/topology.h

+28 −19
Original line number Diff line number Diff line
@@ -140,12 +140,21 @@ extern unsigned long node_remap_size[]; 
	.newidle_idx		= SD_NEWIDLE_IDX,			\

	.wake_idx		= 1,					\

	.forkexec_idx		= SD_FORKEXEC_IDX,			\

	.flags			= SD_LOAD_BALANCE	\

				| SD_BALANCE_EXEC	\

				| SD_BALANCE_FORK	\

				| SD_WAKE_AFFINE	\

				| SD_WAKE_BALANCE	\

				| SD_SERIALIZE,		\

									\

	.flags			= 1*SD_LOAD_BALANCE			\

				| 0*SD_BALANCE_NEWIDLE			\

				| 1*SD_BALANCE_EXEC			\

				| 1*SD_BALANCE_FORK			\

				| 0*SD_WAKE_IDLE			\

				| 1*SD_WAKE_AFFINE			\

				| 1*SD_WAKE_BALANCE			\

				| 0*SD_SHARE_CPUPOWER			\

				| 0*SD_POWERSAVINGS_BALANCE		\

				| 0*SD_SHARE_PKG_RESOURCES		\

				| 1*SD_SERIALIZE			\

				| 0*SD_WAKE_IDLE_FAR			\

				| 0*SD_PREFER_SIBLING			\

				,					\

	.last_balance		= jiffies,				\

	.balance_interval	= 1,					\

}

include/linux/topology.h

+101 −68
Original line number Diff line number Diff line
@@ -90,13 +90,21 @@ int arch_update_cpu_topology(void); 
	.max_interval		= 2,					\

	.busy_factor		= 64,					\

	.imbalance_pct		= 110,					\

	.flags			= SD_LOAD_BALANCE	\

				| SD_BALANCE_NEWIDLE	\

				| SD_BALANCE_FORK	\

				| SD_BALANCE_EXEC	\

				| SD_WAKE_AFFINE	\

				| SD_WAKE_BALANCE	\

				| SD_SHARE_CPUPOWER,	\

									\

	.flags			= 1*SD_LOAD_BALANCE			\

				| 1*SD_BALANCE_NEWIDLE			\

				| 1*SD_BALANCE_EXEC			\

				| 1*SD_BALANCE_FORK			\

				| 0*SD_WAKE_IDLE			\

				| 1*SD_WAKE_AFFINE			\

				| 1*SD_WAKE_BALANCE			\

				| 1*SD_SHARE_CPUPOWER			\

				| 0*SD_POWERSAVINGS_BALANCE		\

				| 0*SD_SHARE_PKG_RESOURCES		\

				| 0*SD_SERIALIZE			\

				| 0*SD_WAKE_IDLE_FAR			\

				| 0*SD_PREFER_SIBLING			\

				,					\

	.last_balance		= jiffies,				\

	.balance_interval	= 1,					\

	.smt_gain		= 1178,	/* 15% */			\
@@ -116,14 +124,21 @@ int arch_update_cpu_topology(void); 
	.busy_idx		= 2,					\

	.wake_idx		= 1,					\

	.forkexec_idx		= 1,					\

	.flags			= SD_LOAD_BALANCE	\

				| SD_BALANCE_FORK	\

				| SD_BALANCE_EXEC	\

				| SD_WAKE_AFFINE	\

				| SD_WAKE_BALANCE	\

				| SD_SHARE_PKG_RESOURCES\

									\

	.flags			= 1*SD_LOAD_BALANCE			\

				| 0*SD_BALANCE_NEWIDLE			\

				| 1*SD_BALANCE_EXEC			\

				| 1*SD_BALANCE_FORK			\

				| 0*SD_WAKE_IDLE			\

				| 1*SD_WAKE_AFFINE			\

				| 1*SD_WAKE_BALANCE			\

				| 0*SD_SHARE_CPUPOWER			\

				| 1*SD_SHARE_PKG_RESOURCES		\

				| 0*SD_SERIALIZE			\

				| 0*SD_WAKE_IDLE_FAR			\

				| sd_balance_for_mc_power()		\

				| sd_power_saving_flags(),\

				| sd_power_saving_flags()		\

				,					\

	.last_balance		= jiffies,				\

	.balance_interval	= 1,					\

}
@@ -143,13 +158,21 @@ int arch_update_cpu_topology(void); 
	.newidle_idx		= 2,					\

	.wake_idx		= 1,					\

	.forkexec_idx		= 1,					\

	.flags			= SD_LOAD_BALANCE	\

				| SD_BALANCE_EXEC	\

				| SD_BALANCE_FORK	\

				| SD_WAKE_AFFINE	\

				| SD_WAKE_BALANCE	\

									\

	.flags			= 1*SD_LOAD_BALANCE			\

				| 0*SD_BALANCE_NEWIDLE			\

				| 1*SD_BALANCE_EXEC			\

				| 1*SD_BALANCE_FORK			\

				| 0*SD_WAKE_IDLE			\

				| 0*SD_WAKE_AFFINE			\

				| 1*SD_WAKE_BALANCE			\

				| 0*SD_SHARE_CPUPOWER			\

				| 0*SD_SHARE_PKG_RESOURCES		\

				| 0*SD_SERIALIZE			\

				| 0*SD_WAKE_IDLE_FAR			\

				| sd_balance_for_package_power()	\

				| sd_power_saving_flags(),\

				| sd_power_saving_flags()		\

				,					\

	.last_balance		= jiffies,				\

	.balance_interval	= 1,					\

}
@@ -164,10 +187,20 @@ int arch_update_cpu_topology(void); 
	.cache_nice_tries	= 1,					\

	.busy_idx		= 3,					\

	.idle_idx		= 3,					\

	.flags			= SD_LOAD_BALANCE	\

				| SD_BALANCE_NEWIDLE	\

				| SD_WAKE_AFFINE	\

				| SD_SERIALIZE,		\

	.flags			= 1*SD_LOAD_BALANCE			\

				| 1*SD_BALANCE_NEWIDLE			\

				| 0*SD_BALANCE_EXEC			\

				| 0*SD_BALANCE_FORK			\

				| 0*SD_WAKE_IDLE			\

				| 1*SD_WAKE_AFFINE			\

				| 0*SD_WAKE_BALANCE			\

				| 0*SD_SHARE_CPUPOWER			\

				| 0*SD_POWERSAVINGS_BALANCE		\

				| 0*SD_SHARE_PKG_RESOURCES		\

				| 1*SD_SERIALIZE			\

				| 0*SD_WAKE_IDLE_FAR			\

				| 0*SD_PREFER_SIBLING			\

				,					\

	.last_balance		= jiffies,				\

	.balance_interval	= 64,					\

}

CRA Git | Maintained and supported by SUSTech CRA and CCSE