Commit 47629f67 authored by Younian Wang's avatar Younian Wang Committed by Shawn Guo
Browse files

clk: hi3798cv200: correct IR clock parent 



The IR clock is sourced from '24m' rather than '100m'.  Correct it.

Signed-off-by: default avatarYounian Wang <wangyounian@hisilicon.com>
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
parent 055d5689

drivers/clk/hisilicon/crg-hi3798cv200.c

+1 −1
Original line number Diff line number Diff line
@@ -244,7 +244,7 @@ static const struct hisi_crg_funcs hi3798cv200_crg_funcs = { 
#define HI3798CV200_SYSCTRL_NR_CLKS 16



static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = {

	{ HISTB_IR_CLK, "clk_ir", "100m",

	{ HISTB_IR_CLK, "clk_ir", "24m",

		CLK_SET_RATE_PARENT, 0x48, 4, 0, },

	{ HISTB_TIMER01_CLK, "clk_timer01", "24m",

		CLK_SET_RATE_PARENT, 0x48, 6, 0, },

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