Unverified Commit 474435a0 authored Sep 02, 2019 by Paul Menzel Committed by Paul Burton Nov 01, 2019

mips/cavium-octeon: Fix typo must in comment



Fixes: 5b3b1688 ("MIPS: Add Cavium OCTEON processor support files to arch/mips/cavium-octeon.")
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Signed-off-by: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Paul Burton <paul.burton@mips.com>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@vger.kernel.org

parent 6fbde6b4

arch/mips/cavium-octeon/setup.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -844,7 +844,7 @@ void __init prom_init(void)
		* BIST should always be enabled when doing a soft reset. L2
		* Cache locking for instance is not cleared unless BIST is
		* enabled. Unfortunately due to a chip errata G-200 for
		* Cn38XX and CN31XX, BIST msut be disabled on these parts.
		* Cn38XX and CN31XX, BIST must be disabled on these parts.
		*/
		if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) \|\|
		OCTEON_IS_MODEL(OCTEON_CN31XX))

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