Commit 4723b20a authored Jul 29, 2013 by David Daney Committed by Ralf Baechle Aug 26, 2013

MIPS: Generate OCTEON3 TLB handlers with the same features as OCTEON2.



OCTEON2 need the same code.

Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5637/


Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent 4122af0a

arch/mips/mm/tlbex.c

+2 −0

Original line number	Diff line number	Diff line
		@@ -85,6 +85,7 @@ static int use_bbit_insns(void)
		case CPU_CAVIUM_OCTEON:
		case CPU_CAVIUM_OCTEON_PLUS:
		case CPU_CAVIUM_OCTEON2:
		case CPU_CAVIUM_OCTEON3:
		return 1;
		default:
		return 0;
		@@ -95,6 +96,7 @@ static int use_lwx_insns(void)
		{
		switch (current_cpu_type()) {
		case CPU_CAVIUM_OCTEON2:
		case CPU_CAVIUM_OCTEON3:
		return 1;
		default:
		return 0;

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