Merge branch 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile (47143b09) · Commits · 戴 / test

MAINTAINERS

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		@@ -5839,6 +5839,8 @@ M: Chris Metcalf <cmetcalf@tilera.com>
		W: http://www.tilera.com/scm/
		S: Supported
		F: arch/tile/
		F: drivers/char/hvc_tile.c
		F: drivers/net/tile/

		TLAN NETWORK DRIVER
		M: Samuel Chessman <chessman@tux.org>

arch/tile/Kconfig

+12 −0

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		@@ -329,6 +329,18 @@ endmenu # Tilera-specific configuration

		menu "Bus options"

		config PCI
		bool "PCI support"
		default y
		select PCI_DOMAINS
		---help---
		Enable PCI root complex support, so PCIe endpoint devices can
		be attached to the Tile chip. Many, but not all, PCI devices
		are supported under Tilera's root complex driver.

		config PCI_DOMAINS
		bool

		config NO_IOMEM
		def_bool !PCI

arch/tile/include/asm/cacheflush.h

+52 −0

Original line number	Diff line number	Diff line
		@@ -137,4 +137,56 @@ static inline void finv_buffer(void *buffer, size_t size)
		mb_incoherent();
		}

		/*
		* Flush & invalidate a VA range that is homed remotely on a single core,
		* waiting until the memory controller holds the flushed values.
		*/
		static inline void finv_buffer_remote(void *buffer, size_t size)
		{
		char *p;
		int i;

		/*
		* Flush and invalidate the buffer out of the local L1/L2
		* and request the home cache to flush and invalidate as well.
		*/
		__finv_buffer(buffer, size);

		/*
		* Wait for the home cache to acknowledge that it has processed
		* all the flush-and-invalidate requests. This does not mean
		* that the flushed data has reached the memory controller yet,
		* but it does mean the home cache is processing the flushes.
		*/
		__insn_mf();

		/*
		* Issue a load to the last cache line, which can't complete
		* until all the previously-issued flushes to the same memory
		* controller have also completed. If we weren't striping
		* memory, that one load would be sufficient, but since we may
		* be, we also need to back up to the last load issued to
		* another memory controller, which would be the point where
		* we crossed an 8KB boundary (the granularity of striping
		* across memory controllers). Keep backing up and doing this
		* until we are before the beginning of the buffer, or have
		* hit all the controllers.
		*/
		for (i = 0, p = (char *)buffer + size - 1;
		i < (1 << CHIP_LOG_NUM_MSHIMS()) && p >= (char *)buffer;
		++i) {
		const unsigned long STRIPE_WIDTH = 8192;

		/* Force a load instruction to issue. */
		(volatile char )p;

		/* Jump to end of previous stripe. */
		p -= STRIPE_WIDTH;
		p = (char *)((unsigned long)p \| (STRIPE_WIDTH - 1));
		}

		/* Wait for the loads (and thus flushes) to have completed. */
		__insn_mf();
		}

		#endif /* _ASM_TILE_CACHEFLUSH_H */

arch/tile/include/asm/io.h

+11 −4

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		@@ -55,9 +55,6 @@ extern void iounmap(volatile void __iomem *addr);
		#define ioremap_writethrough(physaddr, size) ioremap(physaddr, size)
		#define ioremap_fullcache(physaddr, size) ioremap(physaddr, size)

		void __iomem *ioport_map(unsigned long port, unsigned int len);
		extern inline void ioport_unmap(void __iomem *addr) {}

		#define mmiowb()

		/* Conversion between virtual and physical mappings. */
		@@ -189,12 +186,22 @@ static inline void memcpy_toio(volatile void __iomem dst, const void src,
		* we never run, uses them unconditionally.
		*/

		static inline int ioport_panic(void)
		static inline long ioport_panic(void)
		{
		panic("inb/outb and friends do not exist on tile");
		return 0;
		}

		static inline void __iomem *ioport_map(unsigned long port, unsigned int len)
		{
		return (void __iomem *) ioport_panic();
		}

		static inline void ioport_unmap(void __iomem *addr)
		{
		ioport_panic();
		}

		static inline u8 inb(unsigned long addr)
		{
		return ioport_panic();

arch/tile/include/asm/pci-bridge.h

deleted100644 → 0

+0 −117

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		/*
		* Copyright 2010 Tilera Corporation. All Rights Reserved.
		*
		* This program is free software; you can redistribute it and/or
		* modify it under the terms of the GNU General Public License
		* as published by the Free Software Foundation, version 2.
		*
		* This program is distributed in the hope that it will be useful, but
		* WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
		* NON INFRINGEMENT. See the GNU General Public License for
		* more details.
		*/

		#ifndef _ASM_TILE_PCI_BRIDGE_H
		#define _ASM_TILE_PCI_BRIDGE_H

		#include <linux/ioport.h>
		#include <linux/pci.h>

		struct device_node;
		struct pci_controller;

		/*
		* pci_io_base returns the memory address at which you can access
		* the I/O space for PCI bus number `bus' (or NULL on error).
		*/
		extern void __iomem *pci_bus_io_base(unsigned int bus);
		extern unsigned long pci_bus_io_base_phys(unsigned int bus);
		extern unsigned long pci_bus_mem_base_phys(unsigned int bus);

		/* Allocate a new PCI host bridge structure */
		extern struct pci_controller *pcibios_alloc_controller(void);

		/* Helper function for setting up resources */
		extern void pci_init_resource(struct resource *res, unsigned long start,
		unsigned long end, int flags, char *name);

		/* Get the PCI host controller for a bus */
		extern struct pci_controller *pci_bus_to_hose(int bus);

		/*
		* Structure of a PCI controller (host bridge)
		*/
		struct pci_controller {
		int index; /* PCI domain number */
		struct pci_bus *root_bus;

		int first_busno;
		int last_busno;

		int hv_cfg_fd[2]; /* config{0,1} fds for this PCIe controller */
		int hv_mem_fd; /* fd to Hypervisor for MMIO operations */

		struct pci_ops *ops;

		int irq_base; /* Base IRQ from the Hypervisor */
		int plx_gen1; /* flag for PLX Gen 1 configuration */

		/* Address ranges that are routed to this controller/bridge. */
		struct resource mem_resources[3];
		};

		static inline struct pci_controller pci_bus_to_host(struct pci_bus bus)
		{
		return bus->sysdata;
		}

		extern void setup_indirect_pci_nomap(struct pci_controller *hose,
		void __iomem cfg_addr, void __iomem cfg_data);
		extern void setup_indirect_pci(struct pci_controller *hose,
		u32 cfg_addr, u32 cfg_data);
		extern void setup_grackle(struct pci_controller *hose);

		extern unsigned char common_swizzle(struct pci_dev , unsigned char );

		/*
		* The following code swizzles for exactly one bridge. The routine
		* common_swizzle below handles multiple bridges. But there are a
		* some boards that don't follow the PCI spec's suggestion so we
		* break this piece out separately.
		*/
		static inline unsigned char bridge_swizzle(unsigned char pin,
		unsigned char idsel)
		{
		return (((pin-1) + idsel) % 4) + 1;
		}

		/*
		* The following macro is used to lookup irqs in a standard table
		* format for those PPC systems that do not already have PCI
		* interrupts properly routed.
		*/
		/* FIXME - double check this */
		#define PCI_IRQ_TABLE_LOOKUP ({ \
		long _ctl_ = -1; \
		if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot) \
		_ctl_ = pci_irq_table[idsel - min_idsel][pin-1]; \
		_ctl_; \
		})

		/*
		* Scan the buses below a given PCI host bridge and assign suitable
		* resources to all devices found.
		*/
		extern int pciauto_bus_scan(struct pci_controller *, int);

		#ifdef CONFIG_PCI
		extern unsigned long pci_address_to_pio(phys_addr_t address);
		#else
		static inline unsigned long pci_address_to_pio(phys_addr_t address)
		{
		return (unsigned long)-1;
		}
		#endif

		#endif /* _ASM_TILE_PCI_BRIDGE_H */

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