Commit 470e2ca5 authored by Bayan Zabihiyan's avatar Bayan Zabihiyan Committed by Alex Deucher
Browse files

drm/amd/display: Expose OTG_V_TOTAL_MID for HW Diags 



[Why]
Existing HW Features, HW Diags test requested that the
registers be exposed.

[How]
Add V_TOTAL_MID to existing DC structures.
Make sure values are passed down throughout DC
Add Register definition.
Program the additional registers
Add additional Logic for V_TOTAL_CONTROL.

Signed-off-by: default avatarBayan Zabihiyan <bayan.zabihiyan@amd.com>
Reviewed-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Acked-by: default avatarAnthony Koo <Anthony.Koo@amd.com>
Acked-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b1a47f53

drivers/gpu/drm/amd/display/dc/core/dc.c

+3 −1
Original line number Diff line number Diff line
@@ -291,7 +291,9 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc, 
			dc->hwss.set_drr(&pipe,

					1,

					adjust->v_total_min,

					adjust->v_total_max);

					adjust->v_total_max,

					adjust->v_total_mid,

					adjust->v_total_mid_frame_num);



			ret = true;

		}

drivers/gpu/drm/amd/display/dc/dc_hw_types.h

+2 −0
Original line number Diff line number Diff line
@@ -757,6 +757,8 @@ struct crtc_trigger_info { 
struct dc_crtc_timing_adjust {

	uint32_t v_total_min;

	uint32_t v_total_max;

	uint32_t v_total_mid;

	uint32_t v_total_mid_frame_num;

};



#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

+2 −1
Original line number Diff line number Diff line
@@ -1719,7 +1719,8 @@ void dce110_set_safe_displaymarks( 
 ******************************************************************************/



static void set_drr(struct pipe_ctx **pipe_ctx,

		int num_pipes, int vmin, int vmax)

		int num_pipes, unsigned int vmin, unsigned int vmax,

		unsigned int vmid, unsigned int vmid_frame_number)

{

	int i = 0;

	struct drr_params params = {0};

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+4 −1
Original line number Diff line number Diff line
@@ -2747,7 +2747,8 @@ static void dcn10_optimize_bandwidth( 
}



static void dcn10_set_drr(struct pipe_ctx **pipe_ctx,

		int num_pipes, int vmin, int vmax)

		int num_pipes, unsigned int vmin, unsigned int vmax,

		unsigned int vmid, unsigned int vmid_frame_number)

{

	int i = 0;

	struct drr_params params = {0};
@@ -2756,6 +2757,8 @@ static void dcn10_set_drr(struct pipe_ctx **pipe_ctx, 


	params.vertical_total_max = vmax;

	params.vertical_total_min = vmin;

	params.vertical_total_mid = vmid;

	params.vertical_total_mid_frame_num = vmid_frame_number;



	/* TODO: If multiple pipes are to be supported, you need

	 * some GSL stuff. Static screen triggers may be programmed differently

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c

+12 −0
Original line number Diff line number Diff line
@@ -850,6 +850,18 @@ void optc1_set_drr( 
		params->vertical_total_max > 0 &&

		params->vertical_total_min > 0) {



		if (params->vertical_total_mid != 0) {



			REG_SET(OTG_V_TOTAL_MID, 0,

				OTG_V_TOTAL_MID, params->vertical_total_mid - 1);



			REG_UPDATE_2(OTG_V_TOTAL_CONTROL,

					OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,

					OTG_VTOTAL_MID_FRAME_NUM,

					(uint8_t)params->vertical_total_mid_frame_num);



		}



		REG_SET(OTG_V_TOTAL_MAX, 0,

			OTG_V_TOTAL_MAX, params->vertical_total_max - 1);

CRA Git | Maintained and supported by SUSTech CRA and CCSE