Commit 46e840ed authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: replace indirect mmio access in non-dc code path 



all the mmCUR_CONTROL instances are in mmr range and
can be accessd directly by using RREG32/WREG32

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent dec0520a

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

+4 −4
Original line number Diff line number Diff line
@@ -2303,9 +2303,9 @@ static void dce_v10_0_hide_cursor(struct drm_crtc *crtc) 
	struct amdgpu_device *adev = crtc->dev->dev_private;

	u32 tmp;



	tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);

	tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);

	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);

	WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);

	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);

}



static void dce_v10_0_show_cursor(struct drm_crtc *crtc)
@@ -2319,10 +2319,10 @@ static void dce_v10_0_show_cursor(struct drm_crtc *crtc) 
	WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,

	       lower_32_bits(amdgpu_crtc->cursor_addr));



	tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);

	tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);

	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);

	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);

	WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);

	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);

}



static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc,

drivers/gpu/drm/amd/amdgpu/dce_v11_0.c

+4 −4
Original line number Diff line number Diff line
@@ -2382,9 +2382,9 @@ static void dce_v11_0_hide_cursor(struct drm_crtc *crtc) 
	struct amdgpu_device *adev = crtc->dev->dev_private;

	u32 tmp;



	tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);

	tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);

	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);

	WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);

	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);

}



static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
@@ -2398,10 +2398,10 @@ static void dce_v11_0_show_cursor(struct drm_crtc *crtc) 
	WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,

	       lower_32_bits(amdgpu_crtc->cursor_addr));



	tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);

	tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);

	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);

	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);

	WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);

	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);

}



static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

+7 −7
Original line number Diff line number Diff line
@@ -2194,7 +2194,7 @@ static void dce_v6_0_hide_cursor(struct drm_crtc *crtc) 
	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

	struct amdgpu_device *adev = crtc->dev->dev_private;



	WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,

	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,

	       (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |

	       (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
@@ -2211,7 +2211,7 @@ static void dce_v6_0_show_cursor(struct drm_crtc *crtc) 
	WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,

	       lower_32_bits(amdgpu_crtc->cursor_addr));



	WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,

	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,

	       CUR_CONTROL__CURSOR_EN_MASK |

	       (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |

	       (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

+7 −7
Original line number Diff line number Diff line
@@ -2205,7 +2205,7 @@ static void dce_v8_0_hide_cursor(struct drm_crtc *crtc) 
	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

	struct amdgpu_device *adev = crtc->dev->dev_private;



	WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,

	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,

	       (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |

	       (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));

}
@@ -2220,7 +2220,7 @@ static void dce_v8_0_show_cursor(struct drm_crtc *crtc) 
	WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,

	       lower_32_bits(amdgpu_crtc->cursor_addr));



	WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,

	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,

	       CUR_CONTROL__CURSOR_EN_MASK |

	       (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |

	       (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));

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