Commit 46ce10df authored by Miquel Raynal's avatar Miquel Raynal
Browse files

Merge tag 'spi-nor/for-5.3-v2' of... 

Merge tag 'spi-nor/for-5.3-v2' of gitolite.kernel.org:pub/scm/linux/kernel/git/mtd/linux into mtd/next

SPI-NOR core changes:
- add support for the mt25ql02g and w25q16jv flashes
- print error in case of jedec read id fails
- is25lp256: add post BFPT fix to correct the addr_width

SPI NOR controller drivers changes:
- intel-spi: Add support for Intel Elkhart Lake SPI serial flash
- smt32: remove the driver as the driver was replaced by spi-stm32-qspi.c
- cadence-quadspi: add reset control
parents 3bb4bba7 8d1336c2

Documentation/devicetree/bindings/mtd/cadence-quadspi.txt

+5 −0
Original line number Diff line number Diff line
@@ -35,6 +35,9 @@ custom properties: 
		  (qspi_n_ss_out).

- cdns,tslch-ns : Delay in nanoseconds between setting qspi_n_ss_out low

                  and first bit transfer.

- resets	: Must contain an entry for each entry in reset-names.

		  See ../reset/reset.txt for details.

- reset-names	: Must include either "qspi" and/or "qspi-ocp".



Example:
@@ -50,6 +53,8 @@ Example: 
		cdns,fifo-depth = <128>;

		cdns,fifo-width = <4>;

		cdns,trigger-address = <0x00000000>;

		resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>;

		reset-names = "qspi", "qspi-ocp";



		flash0: n25q00@0 {

			...

Documentation/devicetree/bindings/mtd/stm32-quadspi.txt

deleted100644 → 0
+0 −43
Original line number Diff line number Diff line 
* STMicroelectronics Quad Serial Peripheral Interface(QuadSPI)



Required properties:

- compatible: should be "st,stm32f469-qspi"

- reg: the first contains the register location and length.

       the second contains the memory mapping address and length

- reg-names: should contain the reg names "qspi" "qspi_mm"

- interrupts: should contain the interrupt for the device

- clocks: the phandle of the clock needed by the QSPI controller

- A pinctrl must be defined to set pins in mode of operation for QSPI transfer



Optional properties:

- resets: must contain the phandle to the reset controller.



A spi flash must be a child of the nor_flash node and could have some

properties. Also see jedec,spi-nor.txt.



Required properties:

- reg: chip-Select number (QSPI controller may connect 2 nor flashes)

- spi-max-frequency: max frequency of spi bus



Optional property:

- spi-rx-bus-width: see ../spi/spi-bus.txt for the description



Example:



qspi: spi@a0001000 {

	compatible = "st,stm32f469-qspi";

	reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>;

	reg-names = "qspi", "qspi_mm";

	interrupts = <91>;

	resets = <&rcc STM32F4_AHB3_RESET(QSPI)>;

	clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>;

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_qspi0>;



	flash@0 {

		reg = <0>;

		spi-rx-bus-width = <4>;

		spi-max-frequency = <108000000>;

		...

	};

};

drivers/mtd/spi-nor/Kconfig

+0 −7
Original line number Diff line number Diff line
@@ -105,11 +105,4 @@ config SPI_INTEL_SPI_PLATFORM 
	  To compile this driver as a module, choose M here: the module

	  will be called intel-spi-platform.



config SPI_STM32_QUADSPI

	tristate "STM32 Quad SPI controller"

	depends on ARCH_STM32 || COMPILE_TEST

	help

	  This enables support for the STM32 Quad SPI controller.

	  We only connect the NOR to this controller.



endif # MTD_SPI_NOR

drivers/mtd/spi-nor/Makefile

+0 −1
Original line number Diff line number Diff line
@@ -8,4 +8,3 @@ obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o 
obj-$(CONFIG_SPI_INTEL_SPI)	+= intel-spi.o

obj-$(CONFIG_SPI_INTEL_SPI_PCI)	+= intel-spi-pci.o

obj-$(CONFIG_SPI_INTEL_SPI_PLATFORM)	+= intel-spi-platform.o
 
obj-$(CONFIG_SPI_STM32_QUADSPI)	+= stm32-quadspi.o

drivers/mtd/spi-nor/cadence-quadspi.c

+21 −0
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ 
#include <linux/of.h>

#include <linux/platform_device.h>

#include <linux/pm_runtime.h>

#include <linux/reset.h>

#include <linux/sched.h>

#include <linux/spi/spi.h>

#include <linux/timer.h>
@@ -1325,6 +1326,7 @@ static int cqspi_probe(struct platform_device *pdev) 
	struct cqspi_st *cqspi;

	struct resource *res;

	struct resource *res_ahb;

	struct reset_control *rstc, *rstc_ocp;

	const struct cqspi_driver_platdata *ddata;

	int ret;

	int irq;
@@ -1391,6 +1393,25 @@ static int cqspi_probe(struct platform_device *pdev) 
		goto probe_clk_failed;

	}



	/* Obtain QSPI reset control */

	rstc = devm_reset_control_get_optional_exclusive(dev, "qspi");

	if (IS_ERR(rstc)) {

		dev_err(dev, "Cannot get QSPI reset.\n");

		return PTR_ERR(rstc);

	}



	rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp");

	if (IS_ERR(rstc_ocp)) {

		dev_err(dev, "Cannot get QSPI OCP reset.\n");

		return PTR_ERR(rstc_ocp);

	}



	reset_control_assert(rstc);

	reset_control_deassert(rstc);



	reset_control_assert(rstc_ocp);

	reset_control_deassert(rstc_ocp);



	cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);

	ddata  = of_device_get_match_data(dev);

	if (ddata && (ddata->quirks & CQSPI_NEEDS_WR_DELAY))

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